A study on accelerated built-in self test of multi-Gb/s high speed interfaces

Seong Won Kang; Jung Hoon Chun; Young Hyun Jun; Kee Won Kwon

doi:10.1109/NESEA.2011.6144937

A study on accelerated built-in self test of multi-Gb/s high speed interfaces

Seong Won Kang
, Jung Hoon Chun
, Young Hyun Jun
, Kee Won Kwon

Department of Semiconductor Systems Engineering

Research output: Contribution to conference › Paper › peer-review

2 Scopus citations

Abstract

An efficient built-in self test (BIST) method is proposed for accelerated bit error rate (BER) test. The BIST can intentionally generate timing and voltage offsets at the data transmitter in order to measure the timing and voltage margins by drawing stereographic BER diagram on a voltage-time plane. Linear numerical models for 'BER vs. time' and 'BER vs. voltage' are established and verified by the measurement results from various sources. The acceleration test sequence based on the linear model completes the BER test down to 10 ^-15 level in 150msec

Original language	English
DOIs	https://doi.org/10.1109/NESEA.2011.6144937
State	Published - 2011
Event	2011 IEEE 2nd International Conference on Networked Embedded Systems for Enterprise Applications, NESEA 2011 - Fremantle, Perth, WA, Australia Duration: 8 Dec 2011 → 9 Dec 2011

Conference

Conference	2011 IEEE 2nd International Conference on Networked Embedded Systems for Enterprise Applications, NESEA 2011
Country/Territory	Australia
City	Fremantle, Perth, WA
Period	8/12/11 → 9/12/11

Keywords

Acceleration test
BER modeling
BIST
Self-diagnosis
Serial interface

Access to Document

10.1109/NESEA.2011.6144937

Cite this

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title = "A study on accelerated built-in self test of multi-Gb/s high speed interfaces",

abstract = "An efficient built-in self test (BIST) method is proposed for accelerated bit error rate (BER) test. The BIST can intentionally generate timing and voltage offsets at the data transmitter in order to measure the timing and voltage margins by drawing stereographic BER diagram on a voltage-time plane. Linear numerical models for 'BER vs. time' and 'BER vs. voltage' are established and verified by the measurement results from various sources. The acceleration test sequence based on the linear model completes the BER test down to 10 -15 level in 150msec",

keywords = "Acceleration test, BER modeling, BIST, Self-diagnosis, Serial interface",

author = "Kang, \{Seong Won\} and Chun, \{Jung Hoon\} and Jun, \{Young Hyun\} and Kwon, \{Kee Won\}",

year = "2011",

doi = "10.1109/NESEA.2011.6144937",

language = "English",

note = "2011 IEEE 2nd International Conference on Networked Embedded Systems for Enterprise Applications, NESEA 2011 ; Conference date: 08-12-2011 Through 09-12-2011",

}

A study on accelerated built-in self test of multi-Gb/s high speed interfaces. / Kang, Seong Won; Chun, Jung Hoon; Jun, Young Hyun et al.
2011. Paper presented at 2011 IEEE 2nd International Conference on Networked Embedded Systems for Enterprise Applications, NESEA 2011, Fremantle, Perth, WA, Australia.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - A study on accelerated built-in self test of multi-Gb/s high speed interfaces

AU - Kang, Seong Won

AU - Chun, Jung Hoon

AU - Jun, Young Hyun

AU - Kwon, Kee Won

PY - 2011

Y1 - 2011

N2 - An efficient built-in self test (BIST) method is proposed for accelerated bit error rate (BER) test. The BIST can intentionally generate timing and voltage offsets at the data transmitter in order to measure the timing and voltage margins by drawing stereographic BER diagram on a voltage-time plane. Linear numerical models for 'BER vs. time' and 'BER vs. voltage' are established and verified by the measurement results from various sources. The acceleration test sequence based on the linear model completes the BER test down to 10 -15 level in 150msec

AB - An efficient built-in self test (BIST) method is proposed for accelerated bit error rate (BER) test. The BIST can intentionally generate timing and voltage offsets at the data transmitter in order to measure the timing and voltage margins by drawing stereographic BER diagram on a voltage-time plane. Linear numerical models for 'BER vs. time' and 'BER vs. voltage' are established and verified by the measurement results from various sources. The acceleration test sequence based on the linear model completes the BER test down to 10 -15 level in 150msec

KW - Acceleration test

KW - BER modeling

KW - BIST

KW - Self-diagnosis

KW - Serial interface

UR - https://www.scopus.com/pages/publications/84857516208

U2 - 10.1109/NESEA.2011.6144937

DO - 10.1109/NESEA.2011.6144937

M3 - Paper

AN - SCOPUS:84857516208

T2 - 2011 IEEE 2nd International Conference on Networked Embedded Systems for Enterprise Applications, NESEA 2011

Y2 - 8 December 2011 through 9 December 2011

ER -

A study on accelerated built-in self test of multi-Gb/s high speed interfaces

Abstract

Conference

Keywords

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