A Single-Ended Duobinary-PAM4 (PAM7) Transmitter With a 2-Tap Feed-Forward Equalizer

Sanghyeon Park; Jaenam Kim; Jaewoo Park; Junhan Bae; Jung Hoon Chun

doi:10.1109/LSSC.2023.3269043

A Single-Ended Duobinary-PAM4 (PAM7) Transmitter With a 2-Tap Feed-Forward Equalizer

Sanghyeon Park, Jaenam Kim, Jaewoo Park, Junhan Bae, Jung Hoon Chun

Department of Semiconductor Systems Engineering

Research output: Contribution to journal › Article › peer-review

5 Scopus citations

Abstract

A dual-mode transmitter, capable of both pulse amplitude modulation 4-level (PAM4) and duobinary-PAM4 signal generation, has been demonstrated in a 28-nm CMOS technology for memory interfaces. The transmitter utilizes a duobinary-PAM4 encoder that generates 7-level duobinary-PAM4 signals by adding two half-rate PAM4 signals driven by quarter-rate clocks. To generate duobinary-PAM4 signals and incorporate a 2-tap feed-forward equalizer, the proposed transmitter consists of 48 source-series terminated driver segments that are partitioned into four blocks. At 18-Gb/s, the proposed transmitter exhibits energy efficiency of 1.11-pJ/b and 1.66-pJ/b energy in duobinary-PAM4 and PAM4 modes, respectively.

Original language	English
Pages (from-to)	141-144
Number of pages	4
Journal	IEEE Solid-State Circuits Letters
Volume	6
DOIs	https://doi.org/10.1109/LSSC.2023.3269043
State	Published - 2023

Keywords

Duobinary
duobinary-pulse amplitude modulation {4-level} (PAM4)
memory interface
multidrop channel
multilevel signaling
PAM4
transmitter

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/LSSC.2023.3269043

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@article{e132035f39834e30b6da136f4cf33fa0,

title = "A Single-Ended Duobinary-PAM4 (PAM7) Transmitter With a 2-Tap Feed-Forward Equalizer",

abstract = "A dual-mode transmitter, capable of both pulse amplitude modulation 4-level (PAM4) and duobinary-PAM4 signal generation, has been demonstrated in a 28-nm CMOS technology for memory interfaces. The transmitter utilizes a duobinary-PAM4 encoder that generates 7-level duobinary-PAM4 signals by adding two half-rate PAM4 signals driven by quarter-rate clocks. To generate duobinary-PAM4 signals and incorporate a 2-tap feed-forward equalizer, the proposed transmitter consists of 48 source-series terminated driver segments that are partitioned into four blocks. At 18-Gb/s, the proposed transmitter exhibits energy efficiency of 1.11-pJ/b and 1.66-pJ/b energy in duobinary-PAM4 and PAM4 modes, respectively.",

keywords = "Duobinary, duobinary-pulse amplitude modulation \{4-level\} (PAM4), memory interface, multidrop channel, multilevel signaling, PAM4, transmitter",

author = "Sanghyeon Park and Jaenam Kim and Jaewoo Park and Junhan Bae and Chun, \{Jung Hoon\}",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.",

year = "2023",

doi = "10.1109/LSSC.2023.3269043",

language = "English",

volume = "6",

pages = "141--144",

journal = "IEEE Solid-State Circuits Letters",

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T1 - A Single-Ended Duobinary-PAM4 (PAM7) Transmitter With a 2-Tap Feed-Forward Equalizer

AU - Park, Sanghyeon

AU - Kim, Jaenam

AU - Park, Jaewoo

AU - Bae, Junhan

AU - Chun, Jung Hoon

PY - 2023

Y1 - 2023

N2 - A dual-mode transmitter, capable of both pulse amplitude modulation 4-level (PAM4) and duobinary-PAM4 signal generation, has been demonstrated in a 28-nm CMOS technology for memory interfaces. The transmitter utilizes a duobinary-PAM4 encoder that generates 7-level duobinary-PAM4 signals by adding two half-rate PAM4 signals driven by quarter-rate clocks. To generate duobinary-PAM4 signals and incorporate a 2-tap feed-forward equalizer, the proposed transmitter consists of 48 source-series terminated driver segments that are partitioned into four blocks. At 18-Gb/s, the proposed transmitter exhibits energy efficiency of 1.11-pJ/b and 1.66-pJ/b energy in duobinary-PAM4 and PAM4 modes, respectively.

AB - A dual-mode transmitter, capable of both pulse amplitude modulation 4-level (PAM4) and duobinary-PAM4 signal generation, has been demonstrated in a 28-nm CMOS technology for memory interfaces. The transmitter utilizes a duobinary-PAM4 encoder that generates 7-level duobinary-PAM4 signals by adding two half-rate PAM4 signals driven by quarter-rate clocks. To generate duobinary-PAM4 signals and incorporate a 2-tap feed-forward equalizer, the proposed transmitter consists of 48 source-series terminated driver segments that are partitioned into four blocks. At 18-Gb/s, the proposed transmitter exhibits energy efficiency of 1.11-pJ/b and 1.66-pJ/b energy in duobinary-PAM4 and PAM4 modes, respectively.

KW - Duobinary

KW - duobinary-pulse amplitude modulation {4-level} (PAM4)

KW - memory interface

KW - multidrop channel

KW - multilevel signaling

KW - PAM4

KW - transmitter

UR - https://www.scopus.com/pages/publications/85153794183

U2 - 10.1109/LSSC.2023.3269043

DO - 10.1109/LSSC.2023.3269043

M3 - Article

AN - SCOPUS:85153794183

SN - 2573-9603

VL - 6

SP - 141

EP - 144

JO - IEEE Solid-State Circuits Letters

JF - IEEE Solid-State Circuits Letters

ER -

A Single-Ended Duobinary-PAM4 (PAM7) Transmitter With a 2-Tap Feed-Forward Equalizer

Abstract

Keywords

UN SDGs

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