A-Si:H TFT-based gate driver circuit using Q node as both pull-up and hold-down controller

We propose a new gate driver circuit, in which the Q node can be operated as a pull-up either as a hold-down controller. The number of transistors for the QB nodes is reduced because the one QB node can be replaced by the pull-up unit of the Q node. With an additional V_OUT pull-down unit designed using only two transistors and one capacitance, we can control the discharge interval of the V_OUT node to 100% duty ratio. Despite the simplified circuit configuration, the V_OUT characteristic is almost the same as that of a conventional circuit with an AC-driven structure using one Q node, and two or more QB nodes. Our simulation results show that the V_H voltage operates at +28 V from the 1071st to 1080th V_OUT and the rising/falling time is less than 1 μs. To verify the reliability of this circuit, we further confirmed the V_OUT according to the change in the threshold voltage (V_TH). The proposed circuit can be operated even when the V_TH is shifted to +20.5 V from the initial value (V_TH = +1.09 V). Further, the V_OUT characteristic is not degraded although the V_TH was shifted by +18.5 V for the pull-up unit (TFT's ΔV_TH except for pull-up unit: +2 V), and the rising/falling time were confirmed to be less than 3.2 μs.