A Redundancy Eliminated Flip-Flop in 28 nm for Low-Voltage Low-Power Applications

A redundancy eliminated flip-flop (REFF) is presented in 28-nm LP process, targeting wide-range voltage scalability (1-0.3 V). The REFF removes redundant clock transitions to reduce dynamic power consumption and further eliminates redundant transistors with topological and logical methods while keeping it fully static and contention free. The measured power is reduced by 70%/59% with 0%/10% activity at 1-V compared to the TGFF, and 100 dies from five corners were functional down to 0.28 V.