Abstract
A new failure mechanism of PMOSFET devices under BSD conditions is reported and analyzed by investigating various I/O structures. Localized turn-on of the parasitic pnp transistor can be caused by localized charge injection into the body of the PMOSFET. Critical layout parameters affecting this problem are discussed based on 2-D device simulations. A general strategy for avoiding this failure mode is also suggested.
| Original language | English |
|---|---|
| Pages (from-to) | 405-411 |
| Number of pages | 7 |
| Journal | Annual Proceedings - Reliability Physics (Symposium) |
| State | Published - 2004 |
| Externally published | Yes |
| Event | 2004 IEEE International Reliability Physics Symposium Proceedings, 42nd Annual - Phoenix, AZ., United States Duration: 25 Apr 2004 → 29 Apr 2004 |