A Multi-step Approach for Identifying Unknown Defect Patterns on Wafer Bin Map

In this study, we propose a framework for detecting, classifying, and visualizing unknown patterns in semiconductor wafer defect analysis to improve automation in the field. Rapid advancements in semiconductor processes and equipment have led to the emergence of new defect types, most of which are analyzed and identified based on engineers’ experience and judgment. Current approaches struggle with limited labeling, emerging defects, and class imbalance, and although pattern recognition and deep learning techniques have been applied in research, they do not provide a complete solution. We present a method that can quickly detect various emerging defect patterns and ensure high classification accuracy for known defect types. To achieve this, we utilize One Class SVM and Transfer Learning-based ResNet50 backbone, which can be easily implemented on-site. The proposed method uses the one-class SVM method and the validation threshold of each classifier to perform multi-stage unknown defect pattern detection. This approach overcomes the limitations of traditional defect analysis, supporting the identification of new defect types and enhancing engineers’ work efficiency. Furthermore, we employ T-SNE and DBSCAN techniques for dimensionality reduction and visualization, providing high accuracy and dimensionality reduction in identifying new defect patterns. These techniques aid engineers in timely labeling and decision-making, ensuring a more efficient response to emerging defects in the semiconductor industry. Consequently, this study offers a comprehensive framework that addresses the challenges of limited labeling, emerging defects, ultimately improving the performance of semiconductor wafer defect analysis. The effectiveness of the proposed model is evaluated through various experiments.