A low-power dual-PFD phase-rotating PLL with a PFD controller for 5Gb/s serial links

Jun Han Bae; Kyoung Ho Kim; Seok Kim; Kee Won Kwon; Jung Hoon Chun

doi:10.1109/ISCAS.2012.6271715

A low-power dual-PFD phase-rotating PLL with a PFD controller for 5Gb/s serial links

Jun Han Bae, Kyoung Ho Kim, Seok Kim, Kee Won Kwon, Jung Hoon Chun

Department of Semiconductor Systems Engineering

Sungkyunkwan University

Research output: Contribution to conference › Paper › peer-review

10 Scopus citations

Abstract

A novel phase rotating PLL with a dual phase frequency detector (PFD) for 5Gb/s serial links is proposed. By employing a PFD controller, the PLL eliminates a fatal error in phase interpolation due to a nondeterministic characteristic of the PFD. It achieves interpolation between two clocks spaced 180°apart, making the overall structure much simpler with low power consumption. The test chip was implemented in a 65-nm CMOS technology. 8 multi-phase clocks can be simultaneously shifted in steps of 25ps, showing both INL and DNL less than half LSB. Its rms jitter is 0.18ps at 1.25GHz and power consumption is only 3mW from a 1.2V power supply.

Original language	English
Pages	2159-2162
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2012.6271715
State	Published - 2012
Event	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: 20 May 2012 → 23 May 2012

Conference

Conference	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/Territory	Korea, Republic of
City	Seoul
Period	20/05/12 → 23/05/12

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10.1109/ISCAS.2012.6271715

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title = "A low-power dual-PFD phase-rotating PLL with a PFD controller for 5Gb/s serial links",

abstract = "A novel phase rotating PLL with a dual phase frequency detector (PFD) for 5Gb/s serial links is proposed. By employing a PFD controller, the PLL eliminates a fatal error in phase interpolation due to a nondeterministic characteristic of the PFD. It achieves interpolation between two clocks spaced 180°apart, making the overall structure much simpler with low power consumption. The test chip was implemented in a 65-nm CMOS technology. 8 multi-phase clocks can be simultaneously shifted in steps of 25ps, showing both INL and DNL less than half LSB. Its rms jitter is 0.18ps at 1.25GHz and power consumption is only 3mW from a 1.2V power supply.",

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year = "2012",

doi = "10.1109/ISCAS.2012.6271715",

language = "English",

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note = "2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 ; Conference date: 20-05-2012 Through 23-05-2012",

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AU - Bae, Jun Han

AU - Kim, Kyoung Ho

AU - Kim, Seok

AU - Kwon, Kee Won

AU - Chun, Jung Hoon

PY - 2012

Y1 - 2012

N2 - A novel phase rotating PLL with a dual phase frequency detector (PFD) for 5Gb/s serial links is proposed. By employing a PFD controller, the PLL eliminates a fatal error in phase interpolation due to a nondeterministic characteristic of the PFD. It achieves interpolation between two clocks spaced 180°apart, making the overall structure much simpler with low power consumption. The test chip was implemented in a 65-nm CMOS technology. 8 multi-phase clocks can be simultaneously shifted in steps of 25ps, showing both INL and DNL less than half LSB. Its rms jitter is 0.18ps at 1.25GHz and power consumption is only 3mW from a 1.2V power supply.

AB - A novel phase rotating PLL with a dual phase frequency detector (PFD) for 5Gb/s serial links is proposed. By employing a PFD controller, the PLL eliminates a fatal error in phase interpolation due to a nondeterministic characteristic of the PFD. It achieves interpolation between two clocks spaced 180°apart, making the overall structure much simpler with low power consumption. The test chip was implemented in a 65-nm CMOS technology. 8 multi-phase clocks can be simultaneously shifted in steps of 25ps, showing both INL and DNL less than half LSB. Its rms jitter is 0.18ps at 1.25GHz and power consumption is only 3mW from a 1.2V power supply.

UR - https://www.scopus.com/pages/publications/84866615524

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DO - 10.1109/ISCAS.2012.6271715

M3 - Paper

AN - SCOPUS:84866615524

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EP - 2162

T2 - 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012

Y2 - 20 May 2012 through 23 May 2012

ER -

A low-power dual-PFD phase-rotating PLL with a PFD controller for 5Gb/s serial links

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