TY - GEN
T1 - A leakage reduced HVIC with coarse-fine UVLO
AU - Lee, Sungpah
AU - Cho, Kunhee
AU - Lee, Minwoo
AU - Jin, Wookang
PY - 2012
Y1 - 2012
N2 - This paper presents a leakage reduced HVIC using coarse-fine UVLO deploying a coarse UVLO to minimize current consumption of the fine UVLO in idling mode, which overcomes the disadvantage of conventional high side UVLO in HVIC. The proposed HVIC is implemented in 0.5μm Fairchild HDG4D 650V CMOS process. The total current consumption of HVIC including coarse-fine UVLO at 3V power supply is 1μA, which is 10 times smaller current consumption than HVIC with conventional high side UVLO.
AB - This paper presents a leakage reduced HVIC using coarse-fine UVLO deploying a coarse UVLO to minimize current consumption of the fine UVLO in idling mode, which overcomes the disadvantage of conventional high side UVLO in HVIC. The proposed HVIC is implemented in 0.5μm Fairchild HDG4D 650V CMOS process. The total current consumption of HVIC including coarse-fine UVLO at 3V power supply is 1μA, which is 10 times smaller current consumption than HVIC with conventional high side UVLO.
UR - https://www.scopus.com/pages/publications/84873958697
U2 - 10.1109/ISOCC.2012.6406882
DO - 10.1109/ISOCC.2012.6406882
M3 - Conference contribution
AN - SCOPUS:84873958697
SN - 9781467329880
T3 - ISOCC 2012 - 2012 International SoC Design Conference
SP - 408
EP - 411
BT - ISOCC 2012 - 2012 International SoC Design Conference
T2 - 2012 International SoC Design Conference, ISOCC 2012
Y2 - 4 November 2012 through 7 November 2012
ER -