A fully CMOS-compitible 672-bit EEPROM for passive RFID tag application

Jong Min Baek; Jung Hoon Chun; Kee Won Kwon; Jihong Kim; Myung Ho Yoo

doi:10.1109/ASSCC.2010.5716636

A fully CMOS-compitible 672-bit EEPROM for passive RFID tag application

Jong Min Baek
, Jung Hoon Chun
, Kee Won Kwon
, Jihong Kim
, Myung Ho Yoo

Sungkyunkwan University
Samsung

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

9 Scopus citations

Abstract

This paper presents a 672-bit electrically erasable programmable read-only memory (EEPROM) fabricated using a conventional 0.13 μm CMOS process. The write voltages are lowered to 6 V and -4 V using the proposed planar cell structure on the isolated p-wells. The amount of electrons removed from the floating gate is regulated by real-time monitoring to reduce the Vth variation of erased cells. The read and write power dissipations are 2.1 μW and 26 μW, respectively, at room temperature.

Original language	English
Title of host publication	2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Pages	385-388
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2010.5716636
State	Published - 2010
Externally published	Yes
Event	2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 - Beijing, China Duration: 8 Nov 2010 → 10 Nov 2010

Publication series

Name	2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

Conference

Conference	2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Country/Territory	China
City	Beijing
Period	8/11/10 → 10/11/10

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10.1109/ASSCC.2010.5716636

Cite this

@inproceedings{1350da03b12d4933945bea3f478d54cb,

title = "A fully CMOS-compitible 672-bit EEPROM for passive RFID tag application",

abstract = "This paper presents a 672-bit electrically erasable programmable read-only memory (EEPROM) fabricated using a conventional 0.13 μm CMOS process. The write voltages are lowered to 6 V and -4 V using the proposed planar cell structure on the isolated p-wells. The amount of electrons removed from the floating gate is regulated by real-time monitoring to reduce the Vth variation of erased cells. The read and write power dissipations are 2.1 μW and 26 μW, respectively, at room temperature.",

author = "Baek, \{Jong Min\} and Chun, \{Jung Hoon\} and Kwon, \{Kee Won\} and Jihong Kim and Yoo, \{Myung Ho\}",

year = "2010",

doi = "10.1109/ASSCC.2010.5716636",

language = "English",

isbn = "9781424482979",

series = "2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010",

pages = "385--388",

booktitle = "2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010",

note = "2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 ; Conference date: 08-11-2010 Through 10-11-2010",

}

Baek, JM, Chun, JH , Kwon, KW, Kim, J & Yoo, MH 2010, A fully CMOS-compitible 672-bit EEPROM for passive RFID tag application. in 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010., 5716636, 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, pp. 385-388, 2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, Beijing, China, 8/11/10. https://doi.org/10.1109/ASSCC.2010.5716636

A fully CMOS-compitible 672-bit EEPROM for passive RFID tag application. / Baek, Jong Min; Chun, Jung Hoon ; Kwon, Kee Won et al.
2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010. 2010. p. 385-388 5716636 (2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A fully CMOS-compitible 672-bit EEPROM for passive RFID tag application

AU - Baek, Jong Min

AU - Chun, Jung Hoon

AU - Kwon, Kee Won

AU - Kim, Jihong

AU - Yoo, Myung Ho

PY - 2010

Y1 - 2010

N2 - This paper presents a 672-bit electrically erasable programmable read-only memory (EEPROM) fabricated using a conventional 0.13 μm CMOS process. The write voltages are lowered to 6 V and -4 V using the proposed planar cell structure on the isolated p-wells. The amount of electrons removed from the floating gate is regulated by real-time monitoring to reduce the Vth variation of erased cells. The read and write power dissipations are 2.1 μW and 26 μW, respectively, at room temperature.

AB - This paper presents a 672-bit electrically erasable programmable read-only memory (EEPROM) fabricated using a conventional 0.13 μm CMOS process. The write voltages are lowered to 6 V and -4 V using the proposed planar cell structure on the isolated p-wells. The amount of electrons removed from the floating gate is regulated by real-time monitoring to reduce the Vth variation of erased cells. The read and write power dissipations are 2.1 μW and 26 μW, respectively, at room temperature.

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DO - 10.1109/ASSCC.2010.5716636

M3 - Conference contribution

AN - SCOPUS:79952854682

SN - 9781424482979

T3 - 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

SP - 385

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BT - 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

T2 - 2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

Y2 - 8 November 2010 through 10 November 2010

ER -

A fully CMOS-compitible 672-bit EEPROM for passive RFID tag application

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