A fast switching full-CMOS PHS frequency synthesizer with an auxiliary coarse tuning method

Suk Hwan Jang; Sung Kyu Jung; Do Jin Park; Ji Hoon Jung; Jin Kyung Kim; Young Gun Pu; June Young Park; Kang Yoon Lee

doi:10.1109/ESSCIR.2006.307539

A fast switching full-CMOS PHS frequency synthesizer with an auxiliary coarse tuning method

Suk Hwan Jang
, Sung Kyu Jung
, Do Jin Park
, Ji Hoon Jung
, Jin Kyung Kim
, Young Gun Pu
, June Young Park
, Kang Yoon Lee

Konkuk University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. Also, the proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured locktime is about 20μs and the phase noise is -121dBc /√HZ at 600kHz offset. This chip is fabricated with 0.25μm CMOS technology, and the the area is 0.7mm × 2.1mm. The power consumption is 54mW at 2.7V supply voltage.

Original language	English
Title of host publication	ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference
Pages	94-97
Number of pages	4
DOIs	https://doi.org/10.1109/ESSCIR.2006.307539
State	Published - 2006
Externally published	Yes
Event	ESSCIRC 2006 - 32nd European Solid-State Circuits Conference - Montreux, Switzerland Duration: 19 Sep 2006 → 21 Sep 2006

Publication series

Name	ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference

Conference

Conference	ESSCIRC 2006 - 32nd European Solid-State Circuits Conference
Country/Territory	Switzerland
City	Montreux
Period	19/09/06 → 21/09/06

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10.1109/ESSCIR.2006.307539

Cite this

Jang, S. H., Jung, S. K., Park, D. J., Jung, J. H., Kim, J. K., Pu, Y. G., Park, J. Y., & Lee, K. Y. (2006). A fast switching full-CMOS PHS frequency synthesizer with an auxiliary coarse tuning method. In ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference (pp. 94-97). Article 4099712 (ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIR.2006.307539

@inproceedings{70f50b2bb26e493ca5811d186b0c87b1,

title = "A fast switching full-CMOS PHS frequency synthesizer with an auxiliary coarse tuning method",

abstract = "This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. Also, the proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured locktime is about 20μs and the phase noise is -121dBc /√HZ at 600kHz offset. This chip is fabricated with 0.25μm CMOS technology, and the the area is 0.7mm × 2.1mm. The power consumption is 54mW at 2.7V supply voltage.",

author = "Jang, \{Suk Hwan\} and Jung, \{Sung Kyu\} and Park, \{Do Jin\} and Jung, \{Ji Hoon\} and Kim, \{Jin Kyung\} and Pu, \{Young Gun\} and Park, \{June Young\} and Lee, \{Kang Yoon\}",

year = "2006",

doi = "10.1109/ESSCIR.2006.307539",

language = "English",

isbn = "1424403022",

series = "ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference",

pages = "94--97",

booktitle = "ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference",

note = "ESSCIRC 2006 - 32nd European Solid-State Circuits Conference ; Conference date: 19-09-2006 Through 21-09-2006",

}

Jang, SH, Jung, SK, Park, DJ, Jung, JH, Kim, JK, Pu, YG, Park, JY & Lee, KY 2006, A fast switching full-CMOS PHS frequency synthesizer with an auxiliary coarse tuning method. in ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference., 4099712, ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference, pp. 94-97, ESSCIRC 2006 - 32nd European Solid-State Circuits Conference, Montreux, Switzerland, 19/09/06. https://doi.org/10.1109/ESSCIR.2006.307539

A fast switching full-CMOS PHS frequency synthesizer with an auxiliary coarse tuning method. / Jang, Suk Hwan; Jung, Sung Kyu; Park, Do Jin et al.
ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference. 2006. p. 94-97 4099712 (ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - A fast switching full-CMOS PHS frequency synthesizer with an auxiliary coarse tuning method

AU - Jang, Suk Hwan

AU - Jung, Sung Kyu

AU - Park, Do Jin

AU - Jung, Ji Hoon

AU - Kim, Jin Kyung

AU - Pu, Young Gun

AU - Park, June Young

AU - Lee, Kang Yoon

PY - 2006

Y1 - 2006

N2 - This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. Also, the proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured locktime is about 20μs and the phase noise is -121dBc /√HZ at 600kHz offset. This chip is fabricated with 0.25μm CMOS technology, and the the area is 0.7mm × 2.1mm. The power consumption is 54mW at 2.7V supply voltage.

AB - This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. Also, the proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured locktime is about 20μs and the phase noise is -121dBc /√HZ at 600kHz offset. This chip is fabricated with 0.25μm CMOS technology, and the the area is 0.7mm × 2.1mm. The power consumption is 54mW at 2.7V supply voltage.

UR - https://www.scopus.com/pages/publications/51849155237

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DO - 10.1109/ESSCIR.2006.307539

M3 - Conference contribution

AN - SCOPUS:51849155237

SN - 1424403022

SN - 9781424403028

T3 - ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference

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BT - ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference

T2 - ESSCIRC 2006 - 32nd European Solid-State Circuits Conference

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ER -

Jang SH, Jung SK, Park DJ, Jung JH, Kim JK, Pu YG et al. A fast switching full-CMOS PHS frequency synthesizer with an auxiliary coarse tuning method. In ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference. 2006. p. 94-97. 4099712. (ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference). doi: 10.1109/ESSCIR.2006.307539

A fast switching full-CMOS PHS frequency synthesizer with an auxiliary coarse tuning method

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