A dual-mode ground-referenced signaling transceiver with a 3-tap feed-forward equalizer for memory interfaces

This paper describes a ground-referenced signaling (GRS) transceiver with a 3-tap feed-forward equalizer and low frequency mode. In the prototype transceiver, four DQ data lanes share one DQS clock-forwarding lane. To accommodate dynamic voltage and frequency scaling, the proposed transmitter operates in two modes depending on the frequency. The feed-forward equalizer's tap coefficients can be tuned by the pre-charged voltage levels and the number of activated segments. Fabricated in a 28-nm CMOS process, a single DQ block of the proposed GRS transceiver occupies 0.018 mm2. The voltage margin and timing margin were 29.7 mV and 51.6 ps when the equalizer is turned on, but the eye diagram with the equalizer turned off was almost closed with a 13.6-dB channel at at 10 Gb/s. The transceiver achieves BER < 10-13 while dissipating 12.9 mW per lane from a 0.85-V core power supply and 1-V I/O power supply.