A Design of Ultra-Low Power Low-Dropout Regulator for DSRC system

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Abstract

In this paper, we describe Ultra-Low Power (ULP) Low-Dropout Regulator (LDO) circuits for SPI module management in DSRC system. So LDO is Always-On domain. Circuit uses a CMOS 18 nm process. Proposed ULP LDO's output voltage and input voltage is 3.3 V and 1.2 V and total current consumption is 66 nA. By using 2-Transistor voltage reference circuit, Error Amplifier.

Original languageEnglish
Title of host publication34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728132716
DOIs
StatePublished - Jun 2019
Externally publishedYes
Event34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019 - JeJu, Korea, Republic of
Duration: 23 Jun 201926 Jun 2019

Publication series

Name34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019

Conference

Conference34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019
Country/TerritoryKorea, Republic of
CityJeJu
Period23/06/1926/06/19

Keywords

  • Always-on domain
  • SPI management
  • Ultra-Low Power LDO

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