Skip to main navigation Skip to search Skip to main content

A Design of Ultra Low Noise Amplifier through Output Sharing Multi-Input structure using 65nm SOI process technology

  • Sungkyunkwan University

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper describes Design Low Noise Amplifier. This structure satisfies the High Band (1.8G to 2.7GHz) band of LTE RF communication by switching three External Input Inductors. Furthermore, the LNA presented implements proposes Ultra Low Noise techniques via Multi-Input structures. The designed LNA has the highest Gain: 18 dB and the lowest NF: 0.7 dB on 65nm SOI process technology.

Original languageEnglish
Title of host publication2021 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665408578
DOIs
StatePublished - 2021
Event2021 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2021 - Gangwon, Korea, Republic of
Duration: 1 Nov 20213 Nov 2021

Publication series

Name2021 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2021

Conference

Conference2021 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2021
Country/TerritoryKorea, Republic of
CityGangwon
Period1/11/213/11/21

Keywords

  • 65nm SOI process
  • Low Noise Amplifier (LNA)
  • Multi-input
  • Output Sharing
  • Ultra Low Noise
  • Ultra Wide Bandwidth

Fingerprint

Dive into the research topics of 'A Design of Ultra Low Noise Amplifier through Output Sharing Multi-Input structure using 65nm SOI process technology'. Together they form a unique fingerprint.

Cite this