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A design of the frequency synthesizer for UWB application in 0.13 μm RF CMOS process

  • Jin Kyung Kim
  • , Sung Kyu Jung
  • , Ji Hoon Jung
  • , Sang Kyung Sung
  • , Kang Yoon Lee
  • , Chul Nam
  • , Bong Hyuk Park
  • , Sang Sung Choi
  • SiliconHarmony
  • Electronics and Telecommunications Research Institute

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper describes a 3 to 5GHz frequency synthesizer for MB-OFDM (multi-band OFDM) UWB (Ultra-Wideband) application using 0.13μm CMOS process. The frequency synthesizer operates in the band groupl whose center frequencies are 3432MHz, 3960MHz, and 4488MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and prescaler architecture are also presented in this paper. A new coarse tuning scheme that utilizes the MIM capacitance and the varactor is proposed to expand the VCO tuning range. The single PLL and two SSB-mixers consume 75mW from a 1.5V supply. The VCO tuning range is 500MHz. The simulated phase noise of the VCO is -110dBc/Hz at 1MHz offset. The die area is 3 × 2mm2

Original languageEnglish
Title of host publicationProceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008
Pages441-445
Number of pages5
DOIs
StatePublished - 2008
Event4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008 - Hong Kong, SAR, Hong Kong
Duration: 23 Jan 200825 Jan 2008

Publication series

NameProceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008

Conference

Conference4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008
Country/TerritoryHong Kong
CityHong Kong, SAR
Period23/01/0825/01/08

Keywords

  • Frequency synthesizer
  • Phase-locked loop (PLL)
  • Single-sideband (SSB) mixer
  • UWB

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