TY - GEN
T1 - A design of sub-band generator for MB-OFDM UWB application in 0.13 μm RF CMOS process
AU - Park, Joon Sung
AU - Pu, Younggun
AU - Kim, Young Shin
AU - Nam, Chul
AU - Lee, Kang Yoon
PY - 2008
Y1 - 2008
N2 - This paper describes a 3 to 5GHz frequency synthesizer for MB-OFDM (multi-band OFDM) UWB (Ultra- Wideband) application using 0.13um CMOS process. The frequency synthesizer operates in the band group1 whose center frequencies are 3432MHz, 3960MHz, and 4488MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and LO Mixer architecture are also presented in this paper. A new mixed coarse tuning scheme that utilizes the MIM capacitance, the varactor arrays, and the DAC is proposed to expand the VCO tuning range. The frequency synthesizer can also provide the clock for the ADC in baseband modem. So, the PLL for the ADC in the baseband modem can be removed with this frequency synthesizer. The single PLL and two SSB-mixers consume 60mW from a 1.2V supply. The VCO tuning range is 1.2GHz. The simulated phase noise of the VCO is -110dBc/Hz at 1MHz offset. The die area is 3 × 2mm2.
AB - This paper describes a 3 to 5GHz frequency synthesizer for MB-OFDM (multi-band OFDM) UWB (Ultra- Wideband) application using 0.13um CMOS process. The frequency synthesizer operates in the band group1 whose center frequencies are 3432MHz, 3960MHz, and 4488MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and LO Mixer architecture are also presented in this paper. A new mixed coarse tuning scheme that utilizes the MIM capacitance, the varactor arrays, and the DAC is proposed to expand the VCO tuning range. The frequency synthesizer can also provide the clock for the ADC in baseband modem. So, the PLL for the ADC in the baseband modem can be removed with this frequency synthesizer. The single PLL and two SSB-mixers consume 60mW from a 1.2V supply. The VCO tuning range is 1.2GHz. The simulated phase noise of the VCO is -110dBc/Hz at 1MHz offset. The die area is 3 × 2mm2.
UR - https://www.scopus.com/pages/publications/62949231128
U2 - 10.1109/APCCAS.2008.4746369
DO - 10.1109/APCCAS.2008.4746369
M3 - Conference contribution
AN - SCOPUS:62949231128
SN - 9781424423422
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 1712
EP - 1715
BT - Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
T2 - APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
Y2 - 30 November 2008 through 3 December 2008
ER -