A Design of Phase Shifting Phase Locked Loop with Dual Loop Structure for Beamforming Application

Na Hyun Kim; Kang Yoon Lee

doi:10.1109/ICUFN57995.2023.10200955

A Design of Phase Shifting Phase Locked Loop with Dual Loop Structure for Beamforming Application

Na Hyun Kim
, Kang Yoon Lee

SKAIChips

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a structure of Phase-Locked Loop (PLL) that can shift phase by itself. The frequency of the reference clock is 50MHz, and the target frequencies are 5.8 GHz and 4.8 GHz. The PLL structure in this paper has one more Phase-Frequency-Detector (PFD) and one more charge pump. The key idea is to apply two divider output signals with constant delay to each PFD and Charge Pump, then the phase of the output signal of Voltage-Controlled-Oscillator (VCO) is shifted depending on the current of two charge pumps. In this paper, the circuit was designed using a 130nm CMOS process. The phase shifting resolution of the designed PLL is 5.625 degrees.

Original language	English
Title of host publication	ICUFN 2023 - 14th International Conference on Ubiquitous and Future Networks
Publisher	IEEE Computer Society
Pages	752-756
Number of pages	5
ISBN (Electronic)	9798350335385
DOIs	https://doi.org/10.1109/ICUFN57995.2023.10200955
State	Published - 2023
Externally published	Yes
Event	14th International Conference on Ubiquitous and Future Networks, ICUFN 2023 - Paris, France Duration: 4 Jul 2023 → 7 Jul 2023

Publication series

Name	International Conference on Ubiquitous and Future Networks, ICUFN
Volume	2023-July
ISSN (Print)	2165-8528
ISSN (Electronic)	2165-8536

Conference

Conference	14th International Conference on Ubiquitous and Future Networks, ICUFN 2023
Country/Territory	France
City	Paris
Period	4/07/23 → 7/07/23

Keywords

Beamforming
Phase Shifting Phase-Locked Loop
Phase-Locked Loop (PLL)

Access to Document

10.1109/ICUFN57995.2023.10200955

Cite this

Kim, N. H., & Lee, K. Y. (2023). A Design of Phase Shifting Phase Locked Loop with Dual Loop Structure for Beamforming Application. In ICUFN 2023 - 14th International Conference on Ubiquitous and Future Networks (pp. 752-756). (International Conference on Ubiquitous and Future Networks, ICUFN; Vol. 2023-July). IEEE Computer Society. https://doi.org/10.1109/ICUFN57995.2023.10200955

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title = "A Design of Phase Shifting Phase Locked Loop with Dual Loop Structure for Beamforming Application",

abstract = "This paper presents a structure of Phase-Locked Loop (PLL) that can shift phase by itself. The frequency of the reference clock is 50MHz, and the target frequencies are 5.8 GHz and 4.8 GHz. The PLL structure in this paper has one more Phase-Frequency-Detector (PFD) and one more charge pump. The key idea is to apply two divider output signals with constant delay to each PFD and Charge Pump, then the phase of the output signal of Voltage-Controlled-Oscillator (VCO) is shifted depending on the current of two charge pumps. In this paper, the circuit was designed using a 130nm CMOS process. The phase shifting resolution of the designed PLL is 5.625 degrees.",

keywords = "Beamforming, Phase Shifting Phase-Locked Loop, Phase-Locked Loop (PLL)",

author = "Kim, \{Na Hyun\} and Lee, \{Kang Yoon\}",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 14th International Conference on Ubiquitous and Future Networks, ICUFN 2023 ; Conference date: 04-07-2023 Through 07-07-2023",

year = "2023",

doi = "10.1109/ICUFN57995.2023.10200955",

language = "English",

series = "International Conference on Ubiquitous and Future Networks, ICUFN",

publisher = "IEEE Computer Society",

pages = "752--756",

booktitle = "ICUFN 2023 - 14th International Conference on Ubiquitous and Future Networks",

}

Kim, NH & Lee, KY 2023, A Design of Phase Shifting Phase Locked Loop with Dual Loop Structure for Beamforming Application. in ICUFN 2023 - 14th International Conference on Ubiquitous and Future Networks. International Conference on Ubiquitous and Future Networks, ICUFN, vol. 2023-July, IEEE Computer Society, pp. 752-756, 14th International Conference on Ubiquitous and Future Networks, ICUFN 2023, Paris, France, 4/07/23. https://doi.org/10.1109/ICUFN57995.2023.10200955

A Design of Phase Shifting Phase Locked Loop with Dual Loop Structure for Beamforming Application. / Kim, Na Hyun; Lee, Kang Yoon.
ICUFN 2023 - 14th International Conference on Ubiquitous and Future Networks. IEEE Computer Society, 2023. p. 752-756 (International Conference on Ubiquitous and Future Networks, ICUFN; Vol. 2023-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A Design of Phase Shifting Phase Locked Loop with Dual Loop Structure for Beamforming Application

AU - Kim, Na Hyun

AU - Lee, Kang Yoon

PY - 2023

Y1 - 2023

N2 - This paper presents a structure of Phase-Locked Loop (PLL) that can shift phase by itself. The frequency of the reference clock is 50MHz, and the target frequencies are 5.8 GHz and 4.8 GHz. The PLL structure in this paper has one more Phase-Frequency-Detector (PFD) and one more charge pump. The key idea is to apply two divider output signals with constant delay to each PFD and Charge Pump, then the phase of the output signal of Voltage-Controlled-Oscillator (VCO) is shifted depending on the current of two charge pumps. In this paper, the circuit was designed using a 130nm CMOS process. The phase shifting resolution of the designed PLL is 5.625 degrees.

AB - This paper presents a structure of Phase-Locked Loop (PLL) that can shift phase by itself. The frequency of the reference clock is 50MHz, and the target frequencies are 5.8 GHz and 4.8 GHz. The PLL structure in this paper has one more Phase-Frequency-Detector (PFD) and one more charge pump. The key idea is to apply two divider output signals with constant delay to each PFD and Charge Pump, then the phase of the output signal of Voltage-Controlled-Oscillator (VCO) is shifted depending on the current of two charge pumps. In this paper, the circuit was designed using a 130nm CMOS process. The phase shifting resolution of the designed PLL is 5.625 degrees.

KW - Beamforming

KW - Phase Shifting Phase-Locked Loop

KW - Phase-Locked Loop (PLL)

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DO - 10.1109/ICUFN57995.2023.10200955

M3 - Conference contribution

AN - SCOPUS:85169291552

T3 - International Conference on Ubiquitous and Future Networks, ICUFN

SP - 752

EP - 756

BT - ICUFN 2023 - 14th International Conference on Ubiquitous and Future Networks

PB - IEEE Computer Society

T2 - 14th International Conference on Ubiquitous and Future Networks, ICUFN 2023

Y2 - 4 July 2023 through 7 July 2023

ER -

A Design of Phase Shifting Phase Locked Loop with Dual Loop Structure for Beamforming Application

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