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A Design of Low-Power Dynamic Latch Comparator with Adaptive Power Control for12-bit Charge Sharing SAR ADCs

  • Sungkyunkwan University
  • SKAIChips

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents a dynamic latch comparator implemented with Adaptive Power Control (APC) composed of a 12-bit charge-sharing Analog-toDigital Converter (ADC), targeting a low area and low power in integrated RF transmission for ultrasound diagnostic medical devices. The proposed ADC comprises of switches and unit array capacitors with low threshold voltage devices, thereby minimizing the ADC size. The APC structure lowers the consumption of power. The dynamic performance of proposed ADC with a dynamic latch having APC has an Effective Number of Bits (ENOB) of 11.34-bits and Signal and Signal to Noise Distortion Ratio (SNDR) of 70.03 dB at 5 MHz input frequency. The designed ADC is implemented with 0.13 urn CMOS process occupying an area of 1600 μm x 505 μm. The designed SAR ADC draws 1.42 mA current per channel at a sampling rate of 20 MSPS.

Original languageEnglish
Title of host publication2022 International Conference on Electronics, Information, and Communication, ICEIC 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665409346
DOIs
StatePublished - 2022
Event2022 International Conference on Electronics, Information, and Communication, ICEIC 2022 - Jeju, Korea, Republic of
Duration: 6 Feb 20229 Feb 2022

Publication series

Name2022 International Conference on Electronics, Information, and Communication, ICEIC 2022

Conference

Conference2022 International Conference on Electronics, Information, and Communication, ICEIC 2022
Country/TerritoryKorea, Republic of
CityJeju
Period6/02/229/02/22

Keywords

  • Adaptive Dynamic latch comparator
  • charge sharing
  • low power consumption
  • SAR ADCs
  • small area

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