Abstract
This paper proposes the design and implementation of a crystal-less clock generator for low-power, cost-effective sensor transceiver systems. The proposed system integrates a p-poly resistor-based relaxation RC oscillator (RCO), a Fractional-N PLL (W-FPLL) with a wide frequency range and fast settling time, and an on-chip temperature sensor unit (TSU) for temperature compensation. To minimize frequency variation in the RCO, a low target frequency is set, and the frequency range is expanded using the PLL. The W-FPLL supports a wide frequency range from 12.9 MHz to 3.3 GHz. Additionally, temperature-induced frequency variations are compensated by applying the TSU’s digital data to the Delta-Sigma Modulator (DSM), while Piecewise Linear Calibration enhances compensation accuracy. The proposed clock generator achieves a frequency stability of 16.67 ppm/°C under temperature variations. The total system die area is 0.102 mm2. At 3.3 GHz, the system consumes 6.35 mW of total power.
| Original language | English |
|---|---|
| Pages (from-to) | 105995-106002 |
| Number of pages | 8 |
| Journal | IEEE Access |
| Volume | 13 |
| DOIs | |
| State | Published - 2025 |
Keywords
- Crystal-less clock generator
- fractional-N PLL
- on-chip RC oscillator
- sensor transceiver
- temperature compensation