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A COT-based Highly Efficient Hybrid 3-Level Buck Converter for Next-Generation Memory Module Designs

  • Sungkyunkwan University
  • Samsung

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper proposes the design of a useful COT-based high-efficiency Hybrid 3-Level Buck Converter for DRAM Memory Modules. The proposed Buck Converter can achieve an efficiency of 82.8%, surpassing the JEDEC efficiency spec of 82%, even when the DCR of the inductor increases from 10mΩ to 120mΩ. Additionally, it allows for a 75% reduction in the external inductor size, reducing it from 1008 to 0805. Consequently, the overall size of the PMIC block in the DDR5 Memory Module, which includes the PMIC, four inductors, and twelve bulk capacitors, can be reduced from 16.5 x 10.0 mm to 10.5 x 7.0 mm. This reduction in size enables an increase of up to 376uF (47uF 8ea) in the capacitance of High-Density Memory Modules, leading to improved power integrity (PI) performance of the entire Memory Module.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference 2023, ISOCC 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages11-12
Number of pages2
ISBN (Electronic)9798350327038
DOIs
StatePublished - 2023
Event20th International SoC Design Conference, ISOCC 2023 - Jeju, Korea, Republic of
Duration: 25 Oct 202328 Oct 2023

Publication series

NameProceedings - International SoC Design Conference 2023, ISOCC 2023

Conference

Conference20th International SoC Design Conference, ISOCC 2023
Country/TerritoryKorea, Republic of
CityJeju
Period25/10/2328/10/23

Keywords

  • DC-DC Buck Converter
  • DRAM Memory Module
  • High Efficiency

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