A Compact Low-Power Time-Domain Winner-Take-All Circuit

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

In this paper, a compact low-power time-domain winner-take-all (WTA) circuit is proposed. The proposed WTA circuit has a global inhibition signal to inhibit the inputs except the one exceeding the threshold voltage first. The inhibition signal has another important role in preventing redundant transitions in the circuit, resulting in a substantially reduced switching power consumption. Furthermore, the inhibition signal allows the proposed WTA circuit to be configured as a fully parallel structure even for a large number of inputs, achieving compact area and lowlatency operation. The proposed WTA circuit was designed in a 2Snm CMOS process. The performance evaluation results indicated that the proposed WTA circuit improved energy consumption by 88% and layout area by 73.2% as compared to conventional WTA circuits.

Original languageEnglish
Title of host publicationICECS 2023 - 2023 30th IEEE International Conference on Electronics, Circuits and Systems
Subtitle of host publicationTechnosapiens for Saving Humanity
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350326499
DOIs
StatePublished - 2023
Event30th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2023 - Istanbul, Turkey
Duration: 4 Dec 20237 Dec 2023

Publication series

NameICECS 2023 - 2023 30th IEEE International Conference on Electronics, Circuits and Systems: Technosapiens for Saving Humanity

Conference

Conference30th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2023
Country/TerritoryTurkey
CityIstanbul
Period4/12/237/12/23

Keywords

  • convolutional neural networks
  • spiking neural networks
  • time-domain WTA
  • Winner-take-all

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