A Charge-Domain Computation-In-Memory Macro with Versatile All-Around-Wire-Capacitor for Variable-Precision Computation and Array-Embedded DA/AD Conversions

Gicheol Shin; Donguk Seo; Jaerok Kim; Johnny Rhe; Eunyoung Lee; Seonho Kim; Soyoun Jeong; Jong Hwan Ko; Yoonmyung Lee

doi:10.1109/ESSCIRC53450.2021.9567746

A Charge-Domain Computation-In-Memory Macro with Versatile All-Around-Wire-Capacitor for Variable-Precision Computation and Array-Embedded DA/AD Conversions

Gicheol Shin
, Donguk Seo
, Jaerok Kim
, Johnny Rhe
, Eunyoung Lee
, Seonho Kim
, Soyoun Jeong
, Jong Hwan Ko
, Yoonmyung Lee

Department of Electronic and Electrical Engineering

Sungkyunkwan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Scopus citations

Abstract

A charge-domain SRAM-based CIM macro is proposed to implement efficient neural accelerator with variable input/weight/output precisions. A versatile All-Around-Wire-Capacitor (AAWC) is introduced to enable accurate charge-domain MAV operation with 1-5 bit variable-precision weight capability with 10T SRAM cell structure. The AAWC also allows variable-precision array-embedded 1-5 bit digital-to-analog (DA) conversion for input, and 1-6 bit analog-to-digital (AD) conversion for output without additional passive devices. Such array-embedded DA/AD conversion scheme significantly reduces area overhead and simplifies peripheral circuits to achieve high array efficiency while achieving high energy efficiency of 24-330 TOPS/W.

Original language	English
Title of host publication	ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	123-126
Number of pages	4
ISBN (Electronic)	9781665437479
DOIs	https://doi.org/10.1109/ESSCIRC53450.2021.9567746
State	Published - 13 Sep 2021
Event	47th IEEE European Solid State Circuits Conference, ESSCIRC 2021 - Virtual, Online, France Duration: 6 Sep 2021 → 9 Sep 2021

Publication series

Name	ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings

Conference

Conference	47th IEEE European Solid State Circuits Conference, ESSCIRC 2021
Country/Territory	France
City	Virtual, Online
Period	6/09/21 → 9/09/21

Keywords

array-embedded DA/AD conversion
charge-domain
Compute in memory
SRAM
variable-precision

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ESSCIRC53450.2021.9567746

Cite this

Shin, G., Seo, D., Kim, J., Rhe, J., Lee, E., Kim, S., Jeong, S., Ko, J. H., & Lee, Y. (2021). A Charge-Domain Computation-In-Memory Macro with Versatile All-Around-Wire-Capacitor for Variable-Precision Computation and Array-Embedded DA/AD Conversions. In ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings (pp. 123-126). (ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ESSCIRC53450.2021.9567746

Shin, Gicheol ; Seo, Donguk ; Kim, Jaerok et al. / A Charge-Domain Computation-In-Memory Macro with Versatile All-Around-Wire-Capacitor for Variable-Precision Computation and Array-Embedded DA/AD Conversions. ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. pp. 123-126 (ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings).

@inproceedings{1bfbc2510ae34d20a483fa15d880c81d,

title = "A Charge-Domain Computation-In-Memory Macro with Versatile All-Around-Wire-Capacitor for Variable-Precision Computation and Array-Embedded DA/AD Conversions",

abstract = "A charge-domain SRAM-based CIM macro is proposed to implement efficient neural accelerator with variable input/weight/output precisions. A versatile All-Around-Wire-Capacitor (AAWC) is introduced to enable accurate charge-domain MAV operation with 1-5 bit variable-precision weight capability with 10T SRAM cell structure. The AAWC also allows variable-precision array-embedded 1-5 bit digital-to-analog (DA) conversion for input, and 1-6 bit analog-to-digital (AD) conversion for output without additional passive devices. Such array-embedded DA/AD conversion scheme significantly reduces area overhead and simplifies peripheral circuits to achieve high array efficiency while achieving high energy efficiency of 24-330 TOPS/W.",

keywords = "array-embedded DA/AD conversion, charge-domain, Compute in memory, SRAM, variable-precision",

author = "Gicheol Shin and Donguk Seo and Jaerok Kim and Johnny Rhe and Eunyoung Lee and Seonho Kim and Soyoun Jeong and Ko, \{Jong Hwan\} and Yoonmyung Lee",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 47th IEEE European Solid State Circuits Conference, ESSCIRC 2021 ; Conference date: 06-09-2021 Through 09-09-2021",

year = "2021",

month = sep,

day = "13",

doi = "10.1109/ESSCIRC53450.2021.9567746",

language = "English",

series = "ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings",

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Shin, G, Seo, D, Kim, J, Rhe, J, Lee, E, Kim, S, Jeong, S, Ko, JH & Lee, Y 2021, A Charge-Domain Computation-In-Memory Macro with Versatile All-Around-Wire-Capacitor for Variable-Precision Computation and Array-Embedded DA/AD Conversions. in ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings. ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 123-126, 47th IEEE European Solid State Circuits Conference, ESSCIRC 2021, Virtual, Online, France, 6/09/21. https://doi.org/10.1109/ESSCIRC53450.2021.9567746

A Charge-Domain Computation-In-Memory Macro with Versatile All-Around-Wire-Capacitor for Variable-Precision Computation and Array-Embedded DA/AD Conversions. / Shin, Gicheol; Seo, Donguk; Kim, Jaerok et al.
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. p. 123-126 (ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Shin, Gicheol

AU - Seo, Donguk

AU - Kim, Jaerok

AU - Rhe, Johnny

AU - Lee, Eunyoung

AU - Kim, Seonho

AU - Jeong, Soyoun

AU - Ko, Jong Hwan

AU - Lee, Yoonmyung

PY - 2021/9/13

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N2 - A charge-domain SRAM-based CIM macro is proposed to implement efficient neural accelerator with variable input/weight/output precisions. A versatile All-Around-Wire-Capacitor (AAWC) is introduced to enable accurate charge-domain MAV operation with 1-5 bit variable-precision weight capability with 10T SRAM cell structure. The AAWC also allows variable-precision array-embedded 1-5 bit digital-to-analog (DA) conversion for input, and 1-6 bit analog-to-digital (AD) conversion for output without additional passive devices. Such array-embedded DA/AD conversion scheme significantly reduces area overhead and simplifies peripheral circuits to achieve high array efficiency while achieving high energy efficiency of 24-330 TOPS/W.

AB - A charge-domain SRAM-based CIM macro is proposed to implement efficient neural accelerator with variable input/weight/output precisions. A versatile All-Around-Wire-Capacitor (AAWC) is introduced to enable accurate charge-domain MAV operation with 1-5 bit variable-precision weight capability with 10T SRAM cell structure. The AAWC also allows variable-precision array-embedded 1-5 bit digital-to-analog (DA) conversion for input, and 1-6 bit analog-to-digital (AD) conversion for output without additional passive devices. Such array-embedded DA/AD conversion scheme significantly reduces area overhead and simplifies peripheral circuits to achieve high array efficiency while achieving high energy efficiency of 24-330 TOPS/W.

KW - array-embedded DA/AD conversion

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KW - Compute in memory

KW - SRAM

KW - variable-precision

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M3 - Conference contribution

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BT - ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings

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Y2 - 6 September 2021 through 9 September 2021

ER -

Shin G, Seo D, Kim J, Rhe J, Lee E, Kim S et al. A Charge-Domain Computation-In-Memory Macro with Versatile All-Around-Wire-Capacitor for Variable-Precision Computation and Array-Embedded DA/AD Conversions. In ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2021. p. 123-126. (ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings). doi: 10.1109/ESSCIRC53450.2021.9567746

A Charge-Domain Computation-In-Memory Macro with Versatile All-Around-Wire-Capacitor for Variable-Precision Computation and Array-Embedded DA/AD Conversions

Abstract

Publication series

Conference

Keywords

UN SDGs

Access to Document

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