A Calibration-Free 175MHz Bandwidth 60dB SNDR 6th-Order Bandpass Cascaded Time-Interleaved Noise-Shaping SAR ADC with Optimum Zero Placement

Zhiyuan Zhao; Hsiang Wen Chen; Seungheun Song; Taewook Kang; Michael Flynn

doi:10.23919/VLSITechnologyandCir65189.2025.11075147

A Calibration-Free 175MHz Bandwidth 60dB SNDR 6^th-Order Bandpass Cascaded Time-Interleaved Noise-Shaping SAR ADC with Optimum Zero Placement

Zhiyuan Zhao, Hsiang Wen Chen, Seungheun Song, Taewook Kang, Michael Flynn

Department of Semiconductor Convergence Engineering

University of Michigan, Ann Arbor

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A new Cascaded Time-Interleaved (CaTI) Noise-Shaping (NS) SAR ADC combines high-order cascaded NS and new TI bandwidth enhancement techniques to break the bandwidth limitation of NS SAR. The prototype provides 60dB SNDR and 77.5dB SFDR over a 175MHz bandwidth without any calibration, occupies only 0.02mm², and consumes 3.38mW at 1.4GS/s. With an FoMs of 167dB, CaTI NS SAR is a robust and more efficient alternative to conventional TI NS SAR. The prototype has the highest bandwidth of any NS SAR.

Original language	English
Title of host publication	2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9784863488151
DOIs	https://doi.org/10.23919/VLSITechnologyandCir65189.2025.11075147
State	Published - 2025
Event	2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025 - Kyoto, Japan Duration: 8 Jun 2025 → 12 Jun 2025

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562
ISSN (Electronic)	2158-9682

Conference

Conference	2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025
Country/Territory	Japan
City	Kyoto
Period	8/06/25 → 12/06/25

Access to Document

10.23919/VLSITechnologyandCir65189.2025.11075147

Cite this

Zhao, Z., Chen, H. W., Song, S., Kang, T., & Flynn, M. (2025). A Calibration-Free 175MHz Bandwidth 60dB SNDR 6^th-Order Bandpass Cascaded Time-Interleaved Noise-Shaping SAR ADC with Optimum Zero Placement. In 2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025 (Digest of Technical Papers - Symposium on VLSI Technology). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSITechnologyandCir65189.2025.11075147

Zhao, Zhiyuan ; Chen, Hsiang Wen ; Song, Seungheun et al. / A Calibration-Free 175MHz Bandwidth 60dB SNDR 6^th-Order Bandpass Cascaded Time-Interleaved Noise-Shaping SAR ADC with Optimum Zero Placement. 2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025. Institute of Electrical and Electronics Engineers Inc., 2025. (Digest of Technical Papers - Symposium on VLSI Technology).

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title = "A Calibration-Free 175MHz Bandwidth 60dB SNDR 6th-Order Bandpass Cascaded Time-Interleaved Noise-Shaping SAR ADC with Optimum Zero Placement",

abstract = "A new Cascaded Time-Interleaved (CaTI) Noise-Shaping (NS) SAR ADC combines high-order cascaded NS and new TI bandwidth enhancement techniques to break the bandwidth limitation of NS SAR. The prototype provides 60dB SNDR and 77.5dB SFDR over a 175MHz bandwidth without any calibration, occupies only 0.02mm2, and consumes 3.38mW at 1.4GS/s. With an FoMs of 167dB, CaTI NS SAR is a robust and more efficient alternative to conventional TI NS SAR. The prototype has the highest bandwidth of any NS SAR.",

author = "Zhiyuan Zhao and Chen, \{Hsiang Wen\} and Seungheun Song and Taewook Kang and Michael Flynn",

note = "Publisher Copyright: {\textcopyright} 2025 JSAP.; 2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025 ; Conference date: 08-06-2025 Through 12-06-2025",

year = "2025",

doi = "10.23919/VLSITechnologyandCir65189.2025.11075147",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025",

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Zhao, Z, Chen, HW, Song, S, Kang, T & Flynn, M 2025, A Calibration-Free 175MHz Bandwidth 60dB SNDR 6^th-Order Bandpass Cascaded Time-Interleaved Noise-Shaping SAR ADC with Optimum Zero Placement. in 2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025. Digest of Technical Papers - Symposium on VLSI Technology, Institute of Electrical and Electronics Engineers Inc., 2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025, Kyoto, Japan, 8/06/25. https://doi.org/10.23919/VLSITechnologyandCir65189.2025.11075147

A Calibration-Free 175MHz Bandwidth 60dB SNDR 6^th-Order Bandpass Cascaded Time-Interleaved Noise-Shaping SAR ADC with Optimum Zero Placement. / Zhao, Zhiyuan; Chen, Hsiang Wen; Song, Seungheun et al.
2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025. Institute of Electrical and Electronics Engineers Inc., 2025. (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - A new Cascaded Time-Interleaved (CaTI) Noise-Shaping (NS) SAR ADC combines high-order cascaded NS and new TI bandwidth enhancement techniques to break the bandwidth limitation of NS SAR. The prototype provides 60dB SNDR and 77.5dB SFDR over a 175MHz bandwidth without any calibration, occupies only 0.02mm2, and consumes 3.38mW at 1.4GS/s. With an FoMs of 167dB, CaTI NS SAR is a robust and more efficient alternative to conventional TI NS SAR. The prototype has the highest bandwidth of any NS SAR.

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Zhao Z, Chen HW, Song S, Kang T, Flynn M. A Calibration-Free 175MHz Bandwidth 60dB SNDR 6^th-Order Bandpass Cascaded Time-Interleaved Noise-Shaping SAR ADC with Optimum Zero Placement. In 2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025. Institute of Electrical and Electronics Engineers Inc. 2025. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.23919/VLSITechnologyandCir65189.2025.11075147