A 6-Gbps/pin 4.2mW/pin half-deuplex pseudo-LVDS transceiver

This paper presents a half-deuplex pseudo-LVDS (Low Voltage Differential Signaling) transceiver for low-power high-speed interface system. The data rate of 6Gbps/pin and output data window of 147ps pk-pk was demonstrated using a 1.6GHz clock and 196mV swing. The power consumed by the only I/O circuit was measured to be 4.2mW/pin, when connected to a 10pF load, at a 1.2V output supply voltage. The transmitter uses a pseudo LVDS output driver and a commonmode feed-back controller, achieving the reduction of driver currents and the constant common-mode as half voltage level. To achieve the low-transmit jitter, the driver uses the double step pre-emphasis. The receiver employs a shared preamplifier scheme. This scheme ensures transmit power reduction. The proposed LVDS transceiver is fabricated using an 80-nm, DRAM process. It exhibits 25.65ps rms transmitter jitter on the given channel.