A 5.8GHz 9.5 dBm Class-E Power Amplifier for DSRC Applications

Yasser Mohammadi Qaragoez; Imran Ali; Seong Jin Kim; Kang Yoon Lee

doi:10.1109/ISOCC47750.2019.9027646

A 5.8GHz 9.5 dBm Class-E Power Amplifier for DSRC Applications

Yasser Mohammadi Qaragoez
, Imran Ali
, Seong Jin Kim
, Kang Yoon Lee

Sungkyunkwan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

In this paper, a 5.8 GHz Class-E power amplifier with analog delay cell to improve the spurious is presented for dedicated short-range communication (DSRC) transceivers. The power amplifier consists of 2-stage Class-AB as driver stages and a cascode Class-E topology for the PA core. To improve the spurious of the PA an analog delay cell with 128 core cells is implemented which has achieved same fall time and rise time, less area and simplicity in comparison to digital delay cells. Realized in a 0.13-μm CMOS technology, the power amplifier achieves 9.5 dBm and 57 dBc output power and adjacent channel power ratio, respectively. The Occupied bandwidth (OCB) is 64kHz while dissipating 76 mA with 3.3V supply voltage.

Original language	English
Title of host publication	Proceedings - 2019 International SoC Design Conference, ISOCC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	202-203
Number of pages	2
ISBN (Electronic)	9781728124780
DOIs	https://doi.org/10.1109/ISOCC47750.2019.9027646
State	Published - Oct 2019
Externally published	Yes
Event	16th International System-on-Chip Design Conference, ISOCC 2019 - Jeju, Korea, Republic of Duration: 6 Oct 2019 → 9 Oct 2019

Publication series

Name	Proceedings - 2019 International SoC Design Conference, ISOCC 2019

Conference

Conference	16th International System-on-Chip Design Conference, ISOCC 2019
Country/Territory	Korea, Republic of
City	Jeju
Period	6/10/19 → 9/10/19

Keywords

analog delay cell
Class-E
CMOS power amplifier
dedicated short range communication (DSRC)
electronic toll collection system (ETCS)

Access to Document

10.1109/ISOCC47750.2019.9027646

Cite this

Qaragoez, Y. M., Ali, I., Kim, S. J., & Lee, K. Y. (2019). A 5.8GHz 9.5 dBm Class-E Power Amplifier for DSRC Applications. In Proceedings - 2019 International SoC Design Conference, ISOCC 2019 (pp. 202-203). Article 9027646 (Proceedings - 2019 International SoC Design Conference, ISOCC 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC47750.2019.9027646

@inproceedings{f74bda653270449fa306d78e65577a11,

title = "A 5.8GHz 9.5 dBm Class-E Power Amplifier for DSRC Applications",

abstract = "In this paper, a 5.8 GHz Class-E power amplifier with analog delay cell to improve the spurious is presented for dedicated short-range communication (DSRC) transceivers. The power amplifier consists of 2-stage Class-AB as driver stages and a cascode Class-E topology for the PA core. To improve the spurious of the PA an analog delay cell with 128 core cells is implemented which has achieved same fall time and rise time, less area and simplicity in comparison to digital delay cells. Realized in a 0.13-μm CMOS technology, the power amplifier achieves 9.5 dBm and 57 dBc output power and adjacent channel power ratio, respectively. The Occupied bandwidth (OCB) is 64kHz while dissipating 76 mA with 3.3V supply voltage.",

keywords = "analog delay cell, Class-E, CMOS power amplifier, dedicated short range communication (DSRC), electronic toll collection system (ETCS)",

author = "Qaragoez, \{Yasser Mohammadi\} and Imran Ali and Kim, \{Seong Jin\} and Lee, \{Kang Yoon\}",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 16th International System-on-Chip Design Conference, ISOCC 2019 ; Conference date: 06-10-2019 Through 09-10-2019",

year = "2019",

month = oct,

doi = "10.1109/ISOCC47750.2019.9027646",

language = "English",

series = "Proceedings - 2019 International SoC Design Conference, ISOCC 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "202--203",

booktitle = "Proceedings - 2019 International SoC Design Conference, ISOCC 2019",

}

Qaragoez, YM, Ali, I, Kim, SJ & Lee, KY 2019, A 5.8GHz 9.5 dBm Class-E Power Amplifier for DSRC Applications. in Proceedings - 2019 International SoC Design Conference, ISOCC 2019., 9027646, Proceedings - 2019 International SoC Design Conference, ISOCC 2019, Institute of Electrical and Electronics Engineers Inc., pp. 202-203, 16th International System-on-Chip Design Conference, ISOCC 2019, Jeju, Korea, Republic of, 6/10/19. https://doi.org/10.1109/ISOCC47750.2019.9027646

A 5.8GHz 9.5 dBm Class-E Power Amplifier for DSRC Applications. / Qaragoez, Yasser Mohammadi; Ali, Imran; Kim, Seong Jin et al.
Proceedings - 2019 International SoC Design Conference, ISOCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 202-203 9027646 (Proceedings - 2019 International SoC Design Conference, ISOCC 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Qaragoez, Yasser Mohammadi

AU - Ali, Imran

AU - Kim, Seong Jin

AU - Lee, Kang Yoon

PY - 2019/10

Y1 - 2019/10

N2 - In this paper, a 5.8 GHz Class-E power amplifier with analog delay cell to improve the spurious is presented for dedicated short-range communication (DSRC) transceivers. The power amplifier consists of 2-stage Class-AB as driver stages and a cascode Class-E topology for the PA core. To improve the spurious of the PA an analog delay cell with 128 core cells is implemented which has achieved same fall time and rise time, less area and simplicity in comparison to digital delay cells. Realized in a 0.13-μm CMOS technology, the power amplifier achieves 9.5 dBm and 57 dBc output power and adjacent channel power ratio, respectively. The Occupied bandwidth (OCB) is 64kHz while dissipating 76 mA with 3.3V supply voltage.

AB - In this paper, a 5.8 GHz Class-E power amplifier with analog delay cell to improve the spurious is presented for dedicated short-range communication (DSRC) transceivers. The power amplifier consists of 2-stage Class-AB as driver stages and a cascode Class-E topology for the PA core. To improve the spurious of the PA an analog delay cell with 128 core cells is implemented which has achieved same fall time and rise time, less area and simplicity in comparison to digital delay cells. Realized in a 0.13-μm CMOS technology, the power amplifier achieves 9.5 dBm and 57 dBc output power and adjacent channel power ratio, respectively. The Occupied bandwidth (OCB) is 64kHz while dissipating 76 mA with 3.3V supply voltage.

KW - analog delay cell

KW - Class-E

KW - CMOS power amplifier

KW - dedicated short range communication (DSRC)

KW - electronic toll collection system (ETCS)

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BT - Proceedings - 2019 International SoC Design Conference, ISOCC 2019

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A 5.8GHz 9.5 dBm Class-E Power Amplifier for DSRC Applications

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Keywords

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