A 5.2-Gb/s low-swing voltage-mode transmitter with an AC-/DC-Coupled equalizer and a voltage offset generator

Seok Kim; Youngkyun Jeong; Mira Lee; Kee Won Kwon; Jung Hoon Chun

doi:10.1109/TCSI.2013.2262186

A 5.2-Gb/s low-swing voltage-mode transmitter with an AC-/DC-Coupled equalizer and a voltage offset generator

Seok Kim, Youngkyun Jeong, Mira Lee, Kee Won Kwon, Jung Hoon Chun

Research output: Contribution to journal › Article › peer-review

12 Scopus citations

Abstract

This paper describes a voltage-mode transmitter with an AC-/DC-coupled equalizer. A dual-loop regulator controls the tap-weight coefficient for the DC-coupled equalizer while maintaining the output matching condition. An AC-coupling technique is employed to enhance the edge rate and reduce the burden of the DC-coupled equalizer. The transmitter also supports the ability to add a DC differential voltage offset into the output signal so that the voltage margin of the link can be measured. The transmitter was fabricated using a 0.13-um CMOS technology. When 240-V_{\rm PP}, 5.2-Gb/s data are sent over 20-inch FR4 channels, the eye of the received data has a voltage margin of 60 mV and a peak-to-peak jitter of 40 ps. The proposed transmitter consumes 5.86 mW from a 1.2-V supply while operating at 5.2 Gb/s.

Original language	English
Article number	6519975
Pages (from-to)	213-225
Number of pages	13
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	61
Issue number	1
DOIs	https://doi.org/10.1109/TCSI.2013.2262186
State	Published - Jan 2014
Externally published	Yes

Keywords

AC-coupled equalization
impedance matching
tap-weight control
voltage offset generation
voltage-mode transmitter

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10.1109/TCSI.2013.2262186

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title = "A 5.2-Gb/s low-swing voltage-mode transmitter with an AC-/DC-Coupled equalizer and a voltage offset generator",

abstract = "This paper describes a voltage-mode transmitter with an AC-/DC-coupled equalizer. A dual-loop regulator controls the tap-weight coefficient for the DC-coupled equalizer while maintaining the output matching condition. An AC-coupling technique is employed to enhance the edge rate and reduce the burden of the DC-coupled equalizer. The transmitter also supports the ability to add a DC differential voltage offset into the output signal so that the voltage margin of the link can be measured. The transmitter was fabricated using a 0.13-um CMOS technology. When 240-V\textbackslash{}rm PP, 5.2-Gb/s data are sent over 20-inch FR4 channels, the eye of the received data has a voltage margin of 60 mV and a peak-to-peak jitter of 40 ps. The proposed transmitter consumes 5.86 mW from a 1.2-V supply while operating at 5.2 Gb/s.",

keywords = "AC-coupled equalization, impedance matching, tap-weight control, voltage offset generation, voltage-mode transmitter",

author = "Seok Kim and Youngkyun Jeong and Mira Lee and Kwon, \{Kee Won\} and Chun, \{Jung Hoon\}",

year = "2014",

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language = "English",

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T1 - A 5.2-Gb/s low-swing voltage-mode transmitter with an AC-/DC-Coupled equalizer and a voltage offset generator

AU - Kim, Seok

AU - Jeong, Youngkyun

AU - Lee, Mira

AU - Kwon, Kee Won

AU - Chun, Jung Hoon

PY - 2014/1

Y1 - 2014/1

N2 - This paper describes a voltage-mode transmitter with an AC-/DC-coupled equalizer. A dual-loop regulator controls the tap-weight coefficient for the DC-coupled equalizer while maintaining the output matching condition. An AC-coupling technique is employed to enhance the edge rate and reduce the burden of the DC-coupled equalizer. The transmitter also supports the ability to add a DC differential voltage offset into the output signal so that the voltage margin of the link can be measured. The transmitter was fabricated using a 0.13-um CMOS technology. When 240-V\rm PP, 5.2-Gb/s data are sent over 20-inch FR4 channels, the eye of the received data has a voltage margin of 60 mV and a peak-to-peak jitter of 40 ps. The proposed transmitter consumes 5.86 mW from a 1.2-V supply while operating at 5.2 Gb/s.

AB - This paper describes a voltage-mode transmitter with an AC-/DC-coupled equalizer. A dual-loop regulator controls the tap-weight coefficient for the DC-coupled equalizer while maintaining the output matching condition. An AC-coupling technique is employed to enhance the edge rate and reduce the burden of the DC-coupled equalizer. The transmitter also supports the ability to add a DC differential voltage offset into the output signal so that the voltage margin of the link can be measured. The transmitter was fabricated using a 0.13-um CMOS technology. When 240-V\rm PP, 5.2-Gb/s data are sent over 20-inch FR4 channels, the eye of the received data has a voltage margin of 60 mV and a peak-to-peak jitter of 40 ps. The proposed transmitter consumes 5.86 mW from a 1.2-V supply while operating at 5.2 Gb/s.

KW - AC-coupled equalization

KW - impedance matching

KW - tap-weight control

KW - voltage offset generation

KW - voltage-mode transmitter

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DO - 10.1109/TCSI.2013.2262186

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JF - IEEE Transactions on Circuits and Systems I: Regular Papers

IS - 1

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ER -

A 5.2-Gb/s low-swing voltage-mode transmitter with an AC-/DC-Coupled equalizer and a voltage offset generator

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Keywords

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