TY - GEN
T1 - A 5.0-to-12.5-Gb/s, 1.7-pJ/b, 0.66-μs Lock-time Reference-less Sub-sampling CDR with Beat Detection FLL in 28nm CMOS.
AU - Park, Woosung
AU - Jin, Jahoon
AU - Park, Minsu
AU - Jung, Sangdon
AU - Chun, Jung Hoon
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - The primary role of a frequency-locked loop (FLL) is to match the frequency of the recovered clock to the bit-rate clock frequency. Since a perfect match is impossible, there is always a residual frequency even after the FLL is locked. This residual frequency is compensated within the capture range of the phase detector (PD). In practice, the capture range of the PD is usually narrow, and it is desirable to reduce the residual frequency of the FLL as much as possible without sacrificing lock-time, frequency coverage, and energy efficiency.
AB - The primary role of a frequency-locked loop (FLL) is to match the frequency of the recovered clock to the bit-rate clock frequency. Since a perfect match is impossible, there is always a residual frequency even after the FLL is locked. This residual frequency is compensated within the capture range of the phase detector (PD). In practice, the capture range of the PD is usually narrow, and it is desirable to reduce the residual frequency of the FLL as much as possible without sacrificing lock-time, frequency coverage, and energy efficiency.
UR - https://www.scopus.com/pages/publications/85146591122
U2 - 10.1109/A-SSCC56115.2022.9980827
DO - 10.1109/A-SSCC56115.2022.9980827
M3 - Conference contribution
AN - SCOPUS:85146591122
T3 - 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings
BT - 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022
Y2 - 6 November 2022 through 9 November 2022
ER -