A 44.1TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS

Sungju Ryu; Hyungjun Kim; Wooseok Yi; Jongeun Koo; Eunhwan Kim; Yulhwa Kim; Taesu Kim; Jae Joon Kim

doi:10.1109/CICC48029.2020.9075872

A 44.1TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS

Sungju Ryu
, Hyungjun Kim
, Wooseok Yi
, Jongeun Koo
, Eunhwan Kim
, Yulhwa Kim
, Taesu Kim
, Jae Joon Kim

Pohang University of Science and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

10 Scopus citations

Abstract

Supporting variable precision for computing quantized neural network in a hardware accelerator is an efficient way to reduce overall computation time and energy. However, in the previous precision-scalable hardware, bit-reconfiguration logic increases the chip area significantly. In this paper, we demonstrate a compact precision-scalable accelerator chip using bitwise summation and channel-wise aligning schemes. The measurement results show that the peak performance per compute area is improved by 5.1-7.7x and system-level energy-efficiency is improved by up to 64% compared to previous precision-scalable accelerators.

Original language	English
Title of host publication	2020 IEEE Custom Integrated Circuits Conference, CICC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728160313
DOIs	https://doi.org/10.1109/CICC48029.2020.9075872
State	Published - Mar 2020
Externally published	Yes
Event	2020 IEEE Custom Integrated Circuits Conference, CICC 2020 - Boston, United States Duration: 22 Mar 2020 → 25 Mar 2020

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
Volume	2020-March
ISSN (Print)	0886-5930

Conference

Conference	2020 IEEE Custom Integrated Circuits Conference, CICC 2020
Country/Territory	United States
City	Boston
Period	22/03/20 → 25/03/20

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Deep neural network
hardware accelerator. bit-precision scaling
multiply-accumulate unit

Access to Document

10.1109/CICC48029.2020.9075872

Cite this

Ryu, S., Kim, H., Yi, W., Koo, J., Kim, E., Kim, Y., Kim, T., & Kim, J. J. (2020). A 44.1TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS. In 2020 IEEE Custom Integrated Circuits Conference, CICC 2020 Article 9075872 (Proceedings of the Custom Integrated Circuits Conference; Vol. 2020-March). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC48029.2020.9075872

@inproceedings{2d14448f17124e979306b1f4554332ab,

title = "A 44.1TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS",

abstract = "Supporting variable precision for computing quantized neural network in a hardware accelerator is an efficient way to reduce overall computation time and energy. However, in the previous precision-scalable hardware, bit-reconfiguration logic increases the chip area significantly. In this paper, we demonstrate a compact precision-scalable accelerator chip using bitwise summation and channel-wise aligning schemes. The measurement results show that the peak performance per compute area is improved by 5.1-7.7x and system-level energy-efficiency is improved by up to 64\% compared to previous precision-scalable accelerators.",

keywords = "Deep neural network, hardware accelerator. bit-precision scaling, multiply-accumulate unit",

author = "Sungju Ryu and Hyungjun Kim and Wooseok Yi and Jongeun Koo and Eunhwan Kim and Yulhwa Kim and Taesu Kim and Kim, \{Jae Joon\}",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 IEEE Custom Integrated Circuits Conference, CICC 2020 ; Conference date: 22-03-2020 Through 25-03-2020",

year = "2020",

month = mar,

doi = "10.1109/CICC48029.2020.9075872",

language = "English",

series = "Proceedings of the Custom Integrated Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2020 IEEE Custom Integrated Circuits Conference, CICC 2020",

}

Ryu, S, Kim, H, Yi, W, Koo, J, Kim, E, Kim, Y, Kim, T & Kim, JJ 2020, A 44.1TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS. in 2020 IEEE Custom Integrated Circuits Conference, CICC 2020., 9075872, Proceedings of the Custom Integrated Circuits Conference, vol. 2020-March, Institute of Electrical and Electronics Engineers Inc., 2020 IEEE Custom Integrated Circuits Conference, CICC 2020, Boston, United States, 22/03/20. https://doi.org/10.1109/CICC48029.2020.9075872

A 44.1TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS. / Ryu, Sungju; Kim, Hyungjun; Yi, Wooseok et al.
2020 IEEE Custom Integrated Circuits Conference, CICC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9075872 (Proceedings of the Custom Integrated Circuits Conference; Vol. 2020-March).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 44.1TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS

AU - Ryu, Sungju

AU - Kim, Hyungjun

AU - Yi, Wooseok

AU - Koo, Jongeun

AU - Kim, Eunhwan

AU - Kim, Yulhwa

AU - Kim, Taesu

AU - Kim, Jae Joon

PY - 2020/3

Y1 - 2020/3

N2 - Supporting variable precision for computing quantized neural network in a hardware accelerator is an efficient way to reduce overall computation time and energy. However, in the previous precision-scalable hardware, bit-reconfiguration logic increases the chip area significantly. In this paper, we demonstrate a compact precision-scalable accelerator chip using bitwise summation and channel-wise aligning schemes. The measurement results show that the peak performance per compute area is improved by 5.1-7.7x and system-level energy-efficiency is improved by up to 64% compared to previous precision-scalable accelerators.

AB - Supporting variable precision for computing quantized neural network in a hardware accelerator is an efficient way to reduce overall computation time and energy. However, in the previous precision-scalable hardware, bit-reconfiguration logic increases the chip area significantly. In this paper, we demonstrate a compact precision-scalable accelerator chip using bitwise summation and channel-wise aligning schemes. The measurement results show that the peak performance per compute area is improved by 5.1-7.7x and system-level energy-efficiency is improved by up to 64% compared to previous precision-scalable accelerators.

KW - Deep neural network

KW - hardware accelerator. bit-precision scaling

KW - multiply-accumulate unit

UR - https://www.scopus.com/pages/publications/85084470743

U2 - 10.1109/CICC48029.2020.9075872

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M3 - Conference contribution

AN - SCOPUS:85084470743

T3 - Proceedings of the Custom Integrated Circuits Conference

BT - 2020 IEEE Custom Integrated Circuits Conference, CICC 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2020 IEEE Custom Integrated Circuits Conference, CICC 2020

Y2 - 22 March 2020 through 25 March 2020

ER -

A 44.1TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

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