A 32 Gb/s Full duplex Bi-directional Transceiver with Crosstalk Cancellation for Chiplet Interconnections

  • Jae Woo Park
  • , Nicolas Pantano
  • , Geert Van Der Plas
  • , Eric Beyne
  • , Jung Hoon Chun

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Leveraging advanced packaging technology can further improve chip integration by minimizing the dimensions of chip-to-chip interconnections at chiplet interfaces. Nonetheless, the escalation of crosstalk noise, driven by increased speed and routing density, poses a threat to chip functionality. This paper explores the effects of crosstalk in systems through channels with varied lengths and spacings. It also introduces a new high-speed bi-directional transceiver architecture designed to mitigate crosstalk in chiplets or systems featuring short channels and multiple inputs/outputs. Implemented using a 12-nm FinFET process, the proposed transceiver achieves an energy efficiency of 0.46 pJ/bit while operating at 32 Gb/s across a 5-mm channel with 1-μm spacing.

Original languageEnglish
Title of host publicationProceedings - IEEE 74th Electronic Components and Technology Conference, ECTC 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1072-1077
Number of pages6
ISBN (Electronic)9798350375985
DOIs
StatePublished - 2024
Event74th IEEE Electronic Components and Technology Conference, ECTC 2024 - Denver, United States
Duration: 28 May 202431 May 2024

Publication series

NameProceedings - Electronic Components and Technology Conference
ISSN (Print)0569-5503

Conference

Conference74th IEEE Electronic Components and Technology Conference, ECTC 2024
Country/TerritoryUnited States
CityDenver
Period28/05/2431/05/24

Keywords

  • Bi-directional
  • Chip-to-chip
  • crosstalk cancellation
  • transceiver

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