TY - GEN
T1 - A 300 GHz PLL in an InP HBT technology
AU - Seo, Munkyo
AU - Urteaga, Miguel
AU - Rodwell, Mark
AU - Choe, Myung Jun
PY - 2011
Y1 - 2011
N2 - We present a 300 GHz fundamental PLL, based on a 300 GHz VCO, 2:1 dynamic frequency divider, fifth-order sub-harmonic phase detector, and active loop filter, fabricated in an InP HBT technology. The PLL achieves locking from 300.76 to 301.12 GHz, with -23 dBm of output power and -78 dBc/Hz of phase noise at a 100 KHz offset, while consuming 301.6 mW. The PLL occupies 0.84 mm 2 including pads. This work represents the highest frequency PLL reported thus far, 2x to 3x faster than previously reported PLLs.
AB - We present a 300 GHz fundamental PLL, based on a 300 GHz VCO, 2:1 dynamic frequency divider, fifth-order sub-harmonic phase detector, and active loop filter, fabricated in an InP HBT technology. The PLL achieves locking from 300.76 to 301.12 GHz, with -23 dBm of output power and -78 dBc/Hz of phase noise at a 100 KHz offset, while consuming 301.6 mW. The PLL occupies 0.84 mm 2 including pads. This work represents the highest frequency PLL reported thus far, 2x to 3x faster than previously reported PLLs.
KW - dynamic frequency dividers
KW - hetero-junction bipolar transistors
KW - Phase-locked loops
KW - voltage controlled oscillators
UR - https://www.scopus.com/pages/publications/80052325942
U2 - 10.1109/MWSYM.2011.5972924
DO - 10.1109/MWSYM.2011.5972924
M3 - Conference contribution
AN - SCOPUS:80052325942
SN - 9781612847566
T3 - IEEE MTT-S International Microwave Symposium Digest
BT - 2011 IEEE MTT-S International Microwave Symposium, IMS 2011
T2 - 2011 IEEE MTT-S International Microwave Symposium, IMS 2011
Y2 - 5 June 2011 through 10 June 2011
ER -