TY - GEN
T1 - A 23.9 μW 13.6-bit Period Modulation-Based Capacitance-to-Digital Converter with Dynamic Current Mirror Front-end Achieving Capacitor Range of 1 to 68 pF
AU - Lee, Hyeyeon
AU - Seo, Donguk
AU - Woo, Young Jin
AU - Lee, Yoonmyung
AU - Lee, Inhee
AU - Chae, Youngcheol
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - A multi-purpose capacitance-to-digital converter (CDC) needs to cover a wide input range (CIN< 50 pF) for various sensor applications such as a pressure sensor and a strain sensor. Typical CDCs using SAR or delta-sigma modulation have limitations in maintaining their energy-efficiency for such a wide input range, as they require to drive a large reference capacitor (REF<10 pF) with a reference voltage buffer, resulting in high power consumption. On the other hand, CDCs using period-modulation (PM) are good alternative to achieve a large input range [1], [2]. The work in [1] digitizes an input capacitance (CIN) using an iterative delay-chain discharge method. It achieves an excellent energy-efficiency of 0.14 pJ/step, but the effective resolution is limited to 7.9-bit since the charge captured on the CIN is discharged nonlinearly. The work in [2] generates DOUT proportional to a period ratio of the CIN to the CREF and achieves a high resolution of 114 aF at the cost of power and area consumption due to the use of a reference oscillator (140 μW and 0.175 mm2).
AB - A multi-purpose capacitance-to-digital converter (CDC) needs to cover a wide input range (CIN< 50 pF) for various sensor applications such as a pressure sensor and a strain sensor. Typical CDCs using SAR or delta-sigma modulation have limitations in maintaining their energy-efficiency for such a wide input range, as they require to drive a large reference capacitor (REF<10 pF) with a reference voltage buffer, resulting in high power consumption. On the other hand, CDCs using period-modulation (PM) are good alternative to achieve a large input range [1], [2]. The work in [1] digitizes an input capacitance (CIN) using an iterative delay-chain discharge method. It achieves an excellent energy-efficiency of 0.14 pJ/step, but the effective resolution is limited to 7.9-bit since the charge captured on the CIN is discharged nonlinearly. The work in [2] generates DOUT proportional to a period ratio of the CIN to the CREF and achieves a high resolution of 114 aF at the cost of power and area consumption due to the use of a reference oscillator (140 μW and 0.175 mm2).
UR - https://www.scopus.com/pages/publications/85182277631
U2 - 10.1109/A-SSCC58667.2023.10347985
DO - 10.1109/A-SSCC58667.2023.10347985
M3 - Conference contribution
AN - SCOPUS:85182277631
T3 - 2023 IEEE Asian Solid-State Circuits Conference, A-SSCC 2023
BT - 2023 IEEE Asian Solid-State Circuits Conference, A-SSCC 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 19th IEEE Asian Solid-State Circuits Conference, A-SSCC 2023
Y2 - 5 November 2023 through 8 November 2023
ER -