TY - GEN
T1 - A 220-225.9 GHz InP HBT single-chip PLL
AU - Seo, Munkyo
AU - Young, Adam
AU - Urteaga, Miguel
AU - Griffith, Zach
AU - Rodwell, Mark
AU - Choe, Myung Jun
AU - Field, Mark
PY - 2011
Y1 - 2011
N2 - We present a 220 GHz fundamental PLL, based on a 220 GHz VCO, 2:1 dynamic frequency divider, fifth-order sub-harmonic phase detector, active loop filter, and output amplifier, fabricated in an InP HBT technology. The measured PLL locking range was 220.0 to 225.9 GHz, with -83 dBc/Hz of phase noise at a 100 KHz offset, while consuming 465.3 mW. The PLL occupies 1.1 mm2 including pads.
AB - We present a 220 GHz fundamental PLL, based on a 220 GHz VCO, 2:1 dynamic frequency divider, fifth-order sub-harmonic phase detector, active loop filter, and output amplifier, fabricated in an InP HBT technology. The measured PLL locking range was 220.0 to 225.9 GHz, with -83 dBc/Hz of phase noise at a 100 KHz offset, while consuming 465.3 mW. The PLL occupies 1.1 mm2 including pads.
KW - dynamic frequency dividers
KW - hetero-junction bipolar transistors
KW - Phase-locked loops
KW - voltage controlled oscillators
UR - https://www.scopus.com/pages/publications/81455132296
U2 - 10.1109/CSICS.2011.6062495
DO - 10.1109/CSICS.2011.6062495
M3 - Conference contribution
AN - SCOPUS:81455132296
SN - 9781612847122
T3 - Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC
BT - 2011 IEEE Compound Semiconductor Integrated Circuit Symposium
T2 - 2011 33rd IEEE Compound Semiconductor Integrated Circuit Symposium: Integrated Circuits in GaAs, InP, SiGe, GaN and Other Compound Semiconductors, CSICS 2011
Y2 - 16 October 2011 through 19 October 2011
ER -