A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer

Jae Woo Park; Dongsuk Kang; Injae Park; Minsu Park; Xuefan Jin; Kyu Dong Hwang; Dae Han Kwon; Jung Hoon Chun

doi:10.1109/A-SSCC53895.2021.9634179

A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer

Jae Woo Park
, Dongsuk Kang
, Injae Park
, Minsu Park
, Xuefan Jin
, Kyu Dong Hwang
, Dae Han Kwon
, Jung Hoon Chun

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

A duobinary transceiver for Graphics Double Data rate (GDDR) memory interfaces is implemented in a 28nm CMOS technology. The proposed voltage-mode driver complies with the GDDR impedance specifications without sacrificing the ratio of level mismatch (RLM). The quarter-rate time-interleaved successive approximation duobinary receiver reduces the forwarded clock frequency and minimizes the capacitive loading of the front-end analog equalizer. Also, an equalizer adaptation scheme applicable to duobinary signaling is proposed. The transceiver achieves a BER of 10^{-11} at 21 Gb/s with 1.62-mW/Gb/s energy efficiency.

Original language	English
Title of host publication	Proceedings - A-SSCC 2021
Subtitle of host publication	IEEE Asian Solid-State Circuits Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665443500
DOIs	https://doi.org/10.1109/A-SSCC53895.2021.9634179
State	Published - 2021
Externally published	Yes
Event	2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021 - Busan, Korea, Republic of Duration: 7 Nov 2021 → 10 Nov 2021

Publication series

Name	Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference

Conference

Conference	2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021
Country/Territory	Korea, Republic of
City	Busan
Period	7/11/21 → 10/11/21

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Access to Document

10.1109/A-SSCC53895.2021.9634179

Cite this

Park, J. W., Kang, D., Park, I., Park, M., Jin, X., Hwang, K. D., Kwon, D. H., & Chun, J. H. (2021). A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer. In Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference (Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/A-SSCC53895.2021.9634179

@inproceedings{69c13c907a8d433794efb3c24afa4d08,

title = "A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer",

abstract = "A duobinary transceiver for Graphics Double Data rate (GDDR) memory interfaces is implemented in a 28nm CMOS technology. The proposed voltage-mode driver complies with the GDDR impedance specifications without sacrificing the ratio of level mismatch (RLM). The quarter-rate time-interleaved successive approximation duobinary receiver reduces the forwarded clock frequency and minimizes the capacitive loading of the front-end analog equalizer. Also, an equalizer adaptation scheme applicable to duobinary signaling is proposed. The transceiver achieves a BER of 10\textasciicircum{}\{-11\} at 21 Gb/s with 1.62-mW/Gb/s energy efficiency.",

author = "Park, \{Jae Woo\} and Dongsuk Kang and Injae Park and Minsu Park and Xuefan Jin and Hwang, \{Kyu Dong\} and Kwon, \{Dae Han\} and Chun, \{Jung Hoon\}",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021 ; Conference date: 07-11-2021 Through 10-11-2021",

year = "2021",

doi = "10.1109/A-SSCC53895.2021.9634179",

language = "English",

series = "Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Proceedings - A-SSCC 2021",

}

Park, JW, Kang, D, Park, I, Park, M, Jin, X, Hwang, KD, Kwon, DH & Chun, JH 2021, A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer. in Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference. Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., 2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021, Busan, Korea, Republic of, 7/11/21. https://doi.org/10.1109/A-SSCC53895.2021.9634179

A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer. / Park, Jae Woo; Kang, Dongsuk; Park, Injae et al.
Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2021. (Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer

AU - Park, Jae Woo

AU - Kang, Dongsuk

AU - Park, Injae

AU - Park, Minsu

AU - Jin, Xuefan

AU - Hwang, Kyu Dong

AU - Kwon, Dae Han

AU - Chun, Jung Hoon

PY - 2021

Y1 - 2021

N2 - A duobinary transceiver for Graphics Double Data rate (GDDR) memory interfaces is implemented in a 28nm CMOS technology. The proposed voltage-mode driver complies with the GDDR impedance specifications without sacrificing the ratio of level mismatch (RLM). The quarter-rate time-interleaved successive approximation duobinary receiver reduces the forwarded clock frequency and minimizes the capacitive loading of the front-end analog equalizer. Also, an equalizer adaptation scheme applicable to duobinary signaling is proposed. The transceiver achieves a BER of 10^{-11} at 21 Gb/s with 1.62-mW/Gb/s energy efficiency.

AB - A duobinary transceiver for Graphics Double Data rate (GDDR) memory interfaces is implemented in a 28nm CMOS technology. The proposed voltage-mode driver complies with the GDDR impedance specifications without sacrificing the ratio of level mismatch (RLM). The quarter-rate time-interleaved successive approximation duobinary receiver reduces the forwarded clock frequency and minimizes the capacitive loading of the front-end analog equalizer. Also, an equalizer adaptation scheme applicable to duobinary signaling is proposed. The transceiver achieves a BER of 10^{-11} at 21 Gb/s with 1.62-mW/Gb/s energy efficiency.

UR - https://www.scopus.com/pages/publications/85124045241

U2 - 10.1109/A-SSCC53895.2021.9634179

DO - 10.1109/A-SSCC53895.2021.9634179

M3 - Conference contribution

AN - SCOPUS:85124045241

T3 - Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference

BT - Proceedings - A-SSCC 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021

Y2 - 7 November 2021 through 10 November 2021

ER -

Park JW, Kang D, Park I, Park M, Jin X, Hwang KD et al. A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer. In Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference. Institute of Electrical and Electronics Engineers Inc. 2021. (Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference). doi: 10.1109/A-SSCC53895.2021.9634179

A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer

Abstract

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UN SDGs

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