A 21-Gb/s Duobinary Transceiver for GDDR Interfaces With an Adaptive Equalizer

Dongsuk Kang, Jae Woo Park, Injae Park, Min Su Park, Xuefan Jin, Kyu Dong Hwang, Dae Han Kwon, Jung Hoon Chun

Research output: Contribution to journalArticlepeer-review

13 Scopus citations

Abstract

In this article, we propose a duobinary transceiver for graphics double-data-rate (GDDR) memory interfaces. The proposed voltage-mode driver complies with the GDDR impedance specifications without sacrificing the ratio of level mismatch (RLM). The quarter-rate time-interleaved successive approximation duobinary receiver (Rx) reduces the forwarded clock frequency and minimizes the capacitive loading of the front-end analog equalizer (EQ). To compensate for the channel loss, the transmitter is composed of a three-tap feed-forward EQ, and the Rx employs a continuous-time linear EQ. Also, an EQ adaptation scheme applicable to duobinary signaling is proposed. The transceiver achieves a 10-12 bit error rate at 21 Gb/s with 1.42 mW/Gb.

Original languageEnglish
Pages (from-to)3083-3093
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume57
Issue number10
DOIs
StatePublished - 1 Oct 2022
Externally publishedYes

Keywords

  • Adaptive equalizer (EQ)
  • duobinary
  • feed-forward equalizer (FFE)
  • graphics double-data-rate (GDDR)
  • high-speed interface
  • time-interleaving

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