A 16-Way 115–129-GHz High-Power Amplifier With 20.9-dBm P_SAT in 40-nm Bulk CMOS

This article presents a 115–129-GHz power amplifier (PA) with a record P_SAT in 40-nm bulk CMOS. The unit cell is based on a 4-stage differential common-source with cross-coupled capacitors with optimum stage scaling. Interstage matching is performed by asymmetric coupled lines with extra series-shunt sections. Slow wave lines with periodic capacitive loading enable design-rule compliant low-loss output matching network. The overall PA consists of 8 unit-cells, a transmission-line-based low-loss 8:1 power combiner and 1:8 divider. On-wafer measurement shows 21.3 dB peak S₂₁ and 14 GHz 3-dB bandwidth, with 20.9-dBm P_SAT , 17.6-dBm P _1~dB , and 7.6% power-added efficiency (PAE) at 125 GHz at 1.2-V supply. The measured ACLR of the PA is 34.9 dBc with a 100-MHz 5G NR input signal. EVM measurement results show 10% and 6.7% of 16 QAM and 64 QAM, respectively. The PA chip measures 1.34 mm² including pads with 0.69 mm² core area. To the best of our knowledge, the proposed PA yields the highest P_SAT and P _{1 dB} for a D-band PA in CMOS, either bulk or SOI.