@inproceedings{3636a49661be4892a63908762ed49755,
title = "A 12-Gb/s dual-channel transceiver for CMOS image sensor systems",
abstract = "We propose a dual-channel interface architecture that allocates high and low transition-density bit streams to two separate channels. The transmitter utilizes the stacked drivers with charge-recycling to reduce the power consumption. The DC-coupled receiver front-end circuits deal with the common-mode level variations and compensate for the channel loss. The tracked oversampling CDR which realizes fast lock acquisition below 1 baud period and low logic latency is shared by the two channels. Fabricated in a 65-nm low-power CMOS technology, the dual-channel transceiver achieves 12-Gb/s data rate while the transmitter consumes 20.43mW from a 1.2V power supply.",
keywords = "Charge-recycling, CMOS Image Sensor (CIS) System, Dual-channel, Shared CDR, Transceiver",
author = "Kim, \{Sang Hoon\} and Hoon Shin and Youngkyun Jeong and Lee, \{June Hee\} and Jaehyuk Choi and Chun, \{Jung Hoon\}",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 42nd European Solid-State Circuits Conference, ESSCIRC 2016 ; Conference date: 12-09-2016 Through 15-09-2016",
year = "2016",
month = oct,
day = "18",
doi = "10.1109/ESSCIRC.2016.7598300",
language = "English",
series = "European Solid-State Circuits Conference",
publisher = "IEEE Computer Society",
pages = "293--296",
booktitle = "ESSCIRC 2016",
}