A 12-bit 750KS/s 69dB-SNDR 0.48mW Dual-Sampling SAR ADC with reduced C-DAC for wireless charging receiver

Hamed Abbasizadeh; Behnam Samadpoor Rikan; Ji Hun Kang; Hyung Gu Park; Kang Yoon Lee

doi:10.1109/ISOCC.2014.7087556

A 12-bit 750KS/s 69dB-SNDR 0.48mW Dual-Sampling SAR ADC with reduced C-DAC for wireless charging receiver

Hamed Abbasizadeh
, Behnam Samadpoor Rikan
, Ji Hun Kang
, Hyung Gu Park
, Kang Yoon Lee

Department of Electronic and Electrical Engineering

Sungkyunkwan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This paper presents a 12-bit 750KS/s Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for wireless portable device. The scheme of the ADC is based on a Dual-Sampling Capacitive DAC technique, low power dynamic latch comparator with Adaptive Power Control (APC) and bootstrap switch to reduce chip area and power consumption. The proposed 12-bit dual sampling CDAC topology reduces switching energy-efficient compared with 12-bit conventional SAR ADC. The prototype SAR ADC was implemented in Dongbu HiTek 0.18μm CMOS technology and occupies 0.68 mm². The post-layout simulation results show the proposed ADC achieves an ENOB of 11.196 bit at a sampling frequency 750KS/s. It consumes only 0.48mW from a 5.0V supply and achieves the INL and DNL +1.45/-0.65 LSB and +1.0/-1.0 LSB respectively, SNDR 69.16dB, SFDR 78.18dB, and figure of merit (FoM) of 273 fJ/conversion-step.

Original language	English
Title of host publication	ISOCC 2014 - International SoC Design Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	58-59
Number of pages	2
ISBN (Electronic)	9781479951260
DOIs	https://doi.org/10.1109/ISOCC.2014.7087556
State	Published - 16 Apr 2015
Event	11th International SoC Design Conference, ISOCC 2014 - Jeju, Korea, Republic of Duration: 3 Nov 2014 → 6 Nov 2014

Publication series

Name	ISOCC 2014 - International SoC Design Conference

Conference

Conference	11th International SoC Design Conference, ISOCC 2014
Country/Territory	Korea, Republic of
City	Jeju
Period	3/11/14 → 6/11/14

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

bootstrapped switch
comparator
dual sampling
energy-efficient
low power
SAR ADC

Access to Document

10.1109/ISOCC.2014.7087556

Cite this

Abbasizadeh, H., Rikan, B. S., Kang, J. H., Park, H. G., & Lee, K. Y. (2015). A 12-bit 750KS/s 69dB-SNDR 0.48mW Dual-Sampling SAR ADC with reduced C-DAC for wireless charging receiver. In ISOCC 2014 - International SoC Design Conference (pp. 58-59). Article 7087556 (ISOCC 2014 - International SoC Design Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2014.7087556

@inproceedings{2df02d56d3bd4ac6a2b6c3e578587e50,

title = "A 12-bit 750KS/s 69dB-SNDR 0.48mW Dual-Sampling SAR ADC with reduced C-DAC for wireless charging receiver",

abstract = "This paper presents a 12-bit 750KS/s Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for wireless portable device. The scheme of the ADC is based on a Dual-Sampling Capacitive DAC technique, low power dynamic latch comparator with Adaptive Power Control (APC) and bootstrap switch to reduce chip area and power consumption. The proposed 12-bit dual sampling CDAC topology reduces switching energy-efficient compared with 12-bit conventional SAR ADC. The prototype SAR ADC was implemented in Dongbu HiTek 0.18μm CMOS technology and occupies 0.68 mm2. The post-layout simulation results show the proposed ADC achieves an ENOB of 11.196 bit at a sampling frequency 750KS/s. It consumes only 0.48mW from a 5.0V supply and achieves the INL and DNL +1.45/-0.65 LSB and +1.0/-1.0 LSB respectively, SNDR 69.16dB, SFDR 78.18dB, and figure of merit (FoM) of 273 fJ/conversion-step.",

keywords = "bootstrapped switch, comparator, dual sampling, energy-efficient, low power, SAR ADC",

author = "Hamed Abbasizadeh and Rikan, \{Behnam Samadpoor\} and Kang, \{Ji Hun\} and Park, \{Hyung Gu\} and Lee, \{Kang Yoon\}",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 11th International SoC Design Conference, ISOCC 2014 ; Conference date: 03-11-2014 Through 06-11-2014",

year = "2015",

month = apr,

day = "16",

doi = "10.1109/ISOCC.2014.7087556",

language = "English",

series = "ISOCC 2014 - International SoC Design Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "58--59",

booktitle = "ISOCC 2014 - International SoC Design Conference",

}

Abbasizadeh, H, Rikan, BS, Kang, JH, Park, HG & Lee, KY 2015, A 12-bit 750KS/s 69dB-SNDR 0.48mW Dual-Sampling SAR ADC with reduced C-DAC for wireless charging receiver. in ISOCC 2014 - International SoC Design Conference., 7087556, ISOCC 2014 - International SoC Design Conference, Institute of Electrical and Electronics Engineers Inc., pp. 58-59, 11th International SoC Design Conference, ISOCC 2014, Jeju, Korea, Republic of, 3/11/14. https://doi.org/10.1109/ISOCC.2014.7087556

A 12-bit 750KS/s 69dB-SNDR 0.48mW Dual-Sampling SAR ADC with reduced C-DAC for wireless charging receiver. / Abbasizadeh, Hamed; Rikan, Behnam Samadpoor; Kang, Ji Hun et al.
ISOCC 2014 - International SoC Design Conference. Institute of Electrical and Electronics Engineers Inc., 2015. p. 58-59 7087556 (ISOCC 2014 - International SoC Design Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 12-bit 750KS/s 69dB-SNDR 0.48mW Dual-Sampling SAR ADC with reduced C-DAC for wireless charging receiver

AU - Abbasizadeh, Hamed

AU - Rikan, Behnam Samadpoor

AU - Kang, Ji Hun

AU - Park, Hyung Gu

AU - Lee, Kang Yoon

PY - 2015/4/16

Y1 - 2015/4/16

N2 - This paper presents a 12-bit 750KS/s Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for wireless portable device. The scheme of the ADC is based on a Dual-Sampling Capacitive DAC technique, low power dynamic latch comparator with Adaptive Power Control (APC) and bootstrap switch to reduce chip area and power consumption. The proposed 12-bit dual sampling CDAC topology reduces switching energy-efficient compared with 12-bit conventional SAR ADC. The prototype SAR ADC was implemented in Dongbu HiTek 0.18μm CMOS technology and occupies 0.68 mm2. The post-layout simulation results show the proposed ADC achieves an ENOB of 11.196 bit at a sampling frequency 750KS/s. It consumes only 0.48mW from a 5.0V supply and achieves the INL and DNL +1.45/-0.65 LSB and +1.0/-1.0 LSB respectively, SNDR 69.16dB, SFDR 78.18dB, and figure of merit (FoM) of 273 fJ/conversion-step.

AB - This paper presents a 12-bit 750KS/s Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for wireless portable device. The scheme of the ADC is based on a Dual-Sampling Capacitive DAC technique, low power dynamic latch comparator with Adaptive Power Control (APC) and bootstrap switch to reduce chip area and power consumption. The proposed 12-bit dual sampling CDAC topology reduces switching energy-efficient compared with 12-bit conventional SAR ADC. The prototype SAR ADC was implemented in Dongbu HiTek 0.18μm CMOS technology and occupies 0.68 mm2. The post-layout simulation results show the proposed ADC achieves an ENOB of 11.196 bit at a sampling frequency 750KS/s. It consumes only 0.48mW from a 5.0V supply and achieves the INL and DNL +1.45/-0.65 LSB and +1.0/-1.0 LSB respectively, SNDR 69.16dB, SFDR 78.18dB, and figure of merit (FoM) of 273 fJ/conversion-step.

KW - bootstrapped switch

KW - comparator

KW - dual sampling

KW - energy-efficient

KW - low power

KW - SAR ADC

UR - https://www.scopus.com/pages/publications/84929403382

U2 - 10.1109/ISOCC.2014.7087556

DO - 10.1109/ISOCC.2014.7087556

M3 - Conference contribution

AN - SCOPUS:84929403382

T3 - ISOCC 2014 - International SoC Design Conference

SP - 58

EP - 59

BT - ISOCC 2014 - International SoC Design Conference

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 11th International SoC Design Conference, ISOCC 2014

Y2 - 3 November 2014 through 6 November 2014

ER -

Abbasizadeh H, Rikan BS, Kang JH, Park HG, Lee KY. A 12-bit 750KS/s 69dB-SNDR 0.48mW Dual-Sampling SAR ADC with reduced C-DAC for wireless charging receiver. In ISOCC 2014 - International SoC Design Conference. Institute of Electrical and Electronics Engineers Inc. 2015. p. 58-59. 7087556. (ISOCC 2014 - International SoC Design Conference). doi: 10.1109/ISOCC.2014.7087556

A 12-bit 750KS/s 69dB-SNDR 0.48mW Dual-Sampling SAR ADC with reduced C-DAC for wireless charging receiver

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

Other files and links

Fingerprint

Cite this