A 0.75-3.0-Gb/s Dual-Mode Temperature-Tolerant Referenceless CDR with a Deadzone-Compensated Frequency Detector

Jahoon Jin; Xuefan Jin; Jaehong Jung; Kiwon Kwon; Jintae Kim; Jung Hoon Chun

doi:10.1109/JSSC.2018.2856243

A 0.75-3.0-Gb/s Dual-Mode Temperature-Tolerant Referenceless CDR with a Deadzone-Compensated Frequency Detector

Jahoon Jin
, Xuefan Jin
, Jaehong Jung
, Kiwon Kwon
, Jintae Kim
, Jung Hoon Chun

Department of Semiconductor Systems Engineering

Research output: Contribution to journal › Article › peer-review

25 Scopus citations

Abstract

This paper proposes a 750-Mb/s to 3.0-Gb/s dual-mode (full and half rate) referenceless clock and data recovery (CDR) circuit in a 65-nm CMOS process. The dual-mode deadzone-compensated frequency detector (DC-FD) and the digital calibration of both bank and control voltage of voltage-controlled oscillators (VCOs) allow precise frequency acquisition even with high input jitter. The dual-mode scheme extends supported data rates, and the temperature compensation technique allows uninterrupted video transmission with a bit error rate (BER) below 10^-12 over a wide temperature range from-20 °C to 120 °C.

Original language	English
Article number	8425749
Pages (from-to)	2994-3003
Number of pages	10
Journal	IEEE Journal of Solid-State Circuits
Volume	53
Issue number	10
DOIs	https://doi.org/10.1109/JSSC.2018.2856243
State	Published - Oct 2018

Keywords

Clock and data recovery (CDR)
deadzone compensation
dual-mode
frequency acquisition
jitter tolerance (JTOL)
referenceless
temperature compensation

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10.1109/JSSC.2018.2856243

Cite this

@article{56555ec87fb948a182175786f65e404a,

title = "A 0.75-3.0-Gb/s Dual-Mode Temperature-Tolerant Referenceless CDR with a Deadzone-Compensated Frequency Detector",

abstract = "This paper proposes a 750-Mb/s to 3.0-Gb/s dual-mode (full and half rate) referenceless clock and data recovery (CDR) circuit in a 65-nm CMOS process. The dual-mode deadzone-compensated frequency detector (DC-FD) and the digital calibration of both bank and control voltage of voltage-controlled oscillators (VCOs) allow precise frequency acquisition even with high input jitter. The dual-mode scheme extends supported data rates, and the temperature compensation technique allows uninterrupted video transmission with a bit error rate (BER) below 10-12 over a wide temperature range from-20 °C to 120 °C.",

keywords = "Clock and data recovery (CDR), deadzone compensation, dual-mode, frequency acquisition, jitter tolerance (JTOL), referenceless, temperature compensation",

author = "Jahoon Jin and Xuefan Jin and Jaehong Jung and Kiwon Kwon and Jintae Kim and Chun, \{Jung Hoon\}",

note = "Publisher Copyright: {\textcopyright} 1966-2012 IEEE.",

year = "2018",

month = oct,

doi = "10.1109/JSSC.2018.2856243",

language = "English",

volume = "53",

pages = "2994--3003",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "10",

}

TY - JOUR

T1 - A 0.75-3.0-Gb/s Dual-Mode Temperature-Tolerant Referenceless CDR with a Deadzone-Compensated Frequency Detector

AU - Jin, Jahoon

AU - Jin, Xuefan

AU - Jung, Jaehong

AU - Kwon, Kiwon

AU - Kim, Jintae

AU - Chun, Jung Hoon

PY - 2018/10

Y1 - 2018/10

N2 - This paper proposes a 750-Mb/s to 3.0-Gb/s dual-mode (full and half rate) referenceless clock and data recovery (CDR) circuit in a 65-nm CMOS process. The dual-mode deadzone-compensated frequency detector (DC-FD) and the digital calibration of both bank and control voltage of voltage-controlled oscillators (VCOs) allow precise frequency acquisition even with high input jitter. The dual-mode scheme extends supported data rates, and the temperature compensation technique allows uninterrupted video transmission with a bit error rate (BER) below 10-12 over a wide temperature range from-20 °C to 120 °C.

AB - This paper proposes a 750-Mb/s to 3.0-Gb/s dual-mode (full and half rate) referenceless clock and data recovery (CDR) circuit in a 65-nm CMOS process. The dual-mode deadzone-compensated frequency detector (DC-FD) and the digital calibration of both bank and control voltage of voltage-controlled oscillators (VCOs) allow precise frequency acquisition even with high input jitter. The dual-mode scheme extends supported data rates, and the temperature compensation technique allows uninterrupted video transmission with a bit error rate (BER) below 10-12 over a wide temperature range from-20 °C to 120 °C.

KW - Clock and data recovery (CDR)

KW - deadzone compensation

KW - dual-mode

KW - frequency acquisition

KW - jitter tolerance (JTOL)

KW - referenceless

KW - temperature compensation

UR - https://www.scopus.com/pages/publications/85051040616

U2 - 10.1109/JSSC.2018.2856243

DO - 10.1109/JSSC.2018.2856243

M3 - Article

AN - SCOPUS:85051040616

SN - 0018-9200

VL - 53

SP - 2994

EP - 3003

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 10

M1 - 8425749

ER -

A 0.75-3.0-Gb/s Dual-Mode Temperature-Tolerant Referenceless CDR with a Deadzone-Compensated Frequency Detector

Abstract

Keywords

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