A 0.25-μm CMOS 1.9-GHz PHS RF transceiver with a 150-kHz Low-IF architecture

Hoesam Jeong, Byoung Joo Yoo, Cheolkyu Han, Sang Yoon Lee, Kang Yoon Lee, Suhwan Kim, Deog Kyoon Jeong, Wonchan Kim

Research output: Contribution to journalArticlepeer-review

9 Scopus citations

Abstract

We present a 1.9-GHz Personal Handy-phone System (PHS) transceiver, fully integrated and fabricated in 0.25-μm CMOS technology. The receiver is based on a 150-kHz low-IF architecture and meets the fast channel switching and DC-offset cancellation requirements of PHS. It includes a low-noise amplifier (LNA), a downconversion mixer, a complex filter, and a programmable gain amplifier. A fractional-N frequency synthesizer achieves seamless handover with a 25 μs channel switching time and a phase noise of -121 dBc/Hz at a 600-kHz offset frequency, with compliant ACS performance. The receiver provides - 105 dBm sensitivity and 55 dBc ACS at a 600-kHz frequency offset. The transmitter is based on the direct modulation architecture and consists of an upconversion mixer and a pre-driver stage. The gain of the pre-driver is digitally controllable to suit any type of commercial power amplifier. The transmitter shows a 3% EVM and a 65 dBc ACPR at a 600-kHz offset frequency. The whole transceiver occupies 15.2 mm2 and dissipates 70 mA in RX and 44 mA in TX, with a 2.8-V supply.

Original languageEnglish
Pages (from-to)1318-1327
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume42
Issue number6
DOIs
StatePublished - Jun 2007
Externally publishedYes

Keywords

  • Fractional-N synthesizer
  • LNA
  • PHS
  • RF CMOS

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