4-slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8-Gb/s memory controller transceiver

Woo Yeol Shin; Gi Moon Hong; Hyongmin Lee; Jae Duk Han; Kyu Sang Park; Dong Hyuk Lim; Sunkwon Kim; Daeyong Shim; Jung Hoon Chun; Deog Kyoon Jeong; Suhwan Kim

doi:10.1109/TCPMT.2012.2231727

4-slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8-Gb/s memory controller transceiver

Woo Yeol Shin
, Gi Moon Hong
, Hyongmin Lee
, Jae Duk Han
, Kyu Sang Park
, Dong Hyuk Lim
, Sunkwon Kim
, Daeyong Shim
, Jung Hoon Chun
, Deog Kyoon Jeong
, Suhwan Kim

Department of Semiconductor Systems Engineering

Seoul National University

Research output: Contribution to journal › Article › peer-review

3 Scopus citations

Abstract

In this paper, we introduce an impedance-matched bidirectional multidrop (IMBM) DQ bus, together with a 4.8-Gb/s transceiver for a memory controller that supports this bus. Reflective ISI is eliminated at each stub of the IMBM DQ bus by resistive unidirectional impedance matching. A prototype memory controller transceiver is designed and fabricated in a 0.13-μm CMOS process and operates with a 1.2-V supply voltage. Its effectiveness is shown on various multidrop channel configurations. At 4.8 Gb/s, this transceiver with a 4-slot, 8-drop IMBM DQ bus has an eye opening of 0.39 UI in TX mode and 0.58 UI in RX mode, at a threshold of 10^-9 BER, whereas a comparable transceiver with a conventional 4-slot, 8-drop stub series terminated logic has no timing margin under the same test conditions. Our transceiver consumes 14.25 mW/Gb/s per DQ in TX mode, and 13.69 mW/Gb/s per DQ in RX mode.

Original language	English
Article number	6415255
Pages (from-to)	858-869
Number of pages	12
Journal	IEEE Transactions on Components, Packaging and Manufacturing Technology
Volume	3
Issue number	5
DOIs	https://doi.org/10.1109/TCPMT.2012.2231727
State	Published - 2013

Keywords

High-speed interface
impedance matching
memory controller
memory interface
memory transceiver
multidrop DQ bus
stubseries terminated logic

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10.1109/TCPMT.2012.2231727

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Shin, W. Y., Hong, G. M., Lee, H., Han, J. D., Park, K. S., Lim, D. H., Kim, S., Shim, D., Chun, J. H., Jeong, D. K., & Kim, S. (2013). 4-slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8-Gb/s memory controller transceiver. IEEE Transactions on Components, Packaging and Manufacturing Technology, 3(5), 858-869. Article 6415255. https://doi.org/10.1109/TCPMT.2012.2231727

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title = "4-slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8-Gb/s memory controller transceiver",

abstract = "In this paper, we introduce an impedance-matched bidirectional multidrop (IMBM) DQ bus, together with a 4.8-Gb/s transceiver for a memory controller that supports this bus. Reflective ISI is eliminated at each stub of the IMBM DQ bus by resistive unidirectional impedance matching. A prototype memory controller transceiver is designed and fabricated in a 0.13-μm CMOS process and operates with a 1.2-V supply voltage. Its effectiveness is shown on various multidrop channel configurations. At 4.8 Gb/s, this transceiver with a 4-slot, 8-drop IMBM DQ bus has an eye opening of 0.39 UI in TX mode and 0.58 UI in RX mode, at a threshold of 10-9 BER, whereas a comparable transceiver with a conventional 4-slot, 8-drop stub series terminated logic has no timing margin under the same test conditions. Our transceiver consumes 14.25 mW/Gb/s per DQ in TX mode, and 13.69 mW/Gb/s per DQ in RX mode.",

keywords = "High-speed interface, impedance matching, memory controller, memory interface, memory transceiver, multidrop DQ bus, stubseries terminated logic",

author = "Shin, \{Woo Yeol\} and Hong, \{Gi Moon\} and Hyongmin Lee and Han, \{Jae Duk\} and Park, \{Kyu Sang\} and Lim, \{Dong Hyuk\} and Sunkwon Kim and Daeyong Shim and Chun, \{Jung Hoon\} and Jeong, \{Deog Kyoon\} and Suhwan Kim",

year = "2013",

doi = "10.1109/TCPMT.2012.2231727",

language = "English",

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pages = "858--869",

journal = "IEEE Transactions on Components, Packaging and Manufacturing Technology",

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number = "5",

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Shin, WY, Hong, GM, Lee, H, Han, JD, Park, KS, Lim, DH, Kim, S, Shim, D, Chun, JH, Jeong, DK & Kim, S 2013, '4-slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8-Gb/s memory controller transceiver', IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 3, no. 5, 6415255, pp. 858-869. https://doi.org/10.1109/TCPMT.2012.2231727

TY - JOUR

T1 - 4-slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8-Gb/s memory controller transceiver

AU - Shin, Woo Yeol

AU - Hong, Gi Moon

AU - Lee, Hyongmin

AU - Han, Jae Duk

AU - Park, Kyu Sang

AU - Lim, Dong Hyuk

AU - Kim, Sunkwon

AU - Shim, Daeyong

AU - Chun, Jung Hoon

AU - Jeong, Deog Kyoon

AU - Kim, Suhwan

PY - 2013

Y1 - 2013

N2 - In this paper, we introduce an impedance-matched bidirectional multidrop (IMBM) DQ bus, together with a 4.8-Gb/s transceiver for a memory controller that supports this bus. Reflective ISI is eliminated at each stub of the IMBM DQ bus by resistive unidirectional impedance matching. A prototype memory controller transceiver is designed and fabricated in a 0.13-μm CMOS process and operates with a 1.2-V supply voltage. Its effectiveness is shown on various multidrop channel configurations. At 4.8 Gb/s, this transceiver with a 4-slot, 8-drop IMBM DQ bus has an eye opening of 0.39 UI in TX mode and 0.58 UI in RX mode, at a threshold of 10-9 BER, whereas a comparable transceiver with a conventional 4-slot, 8-drop stub series terminated logic has no timing margin under the same test conditions. Our transceiver consumes 14.25 mW/Gb/s per DQ in TX mode, and 13.69 mW/Gb/s per DQ in RX mode.

AB - In this paper, we introduce an impedance-matched bidirectional multidrop (IMBM) DQ bus, together with a 4.8-Gb/s transceiver for a memory controller that supports this bus. Reflective ISI is eliminated at each stub of the IMBM DQ bus by resistive unidirectional impedance matching. A prototype memory controller transceiver is designed and fabricated in a 0.13-μm CMOS process and operates with a 1.2-V supply voltage. Its effectiveness is shown on various multidrop channel configurations. At 4.8 Gb/s, this transceiver with a 4-slot, 8-drop IMBM DQ bus has an eye opening of 0.39 UI in TX mode and 0.58 UI in RX mode, at a threshold of 10-9 BER, whereas a comparable transceiver with a conventional 4-slot, 8-drop stub series terminated logic has no timing margin under the same test conditions. Our transceiver consumes 14.25 mW/Gb/s per DQ in TX mode, and 13.69 mW/Gb/s per DQ in RX mode.

KW - High-speed interface

KW - impedance matching

KW - memory controller

KW - memory interface

KW - memory transceiver

KW - multidrop DQ bus

KW - stubseries terminated logic

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DO - 10.1109/TCPMT.2012.2231727

M3 - Article

AN - SCOPUS:84877580223

SN - 2156-3950

VL - 3

SP - 858

EP - 869

JO - IEEE Transactions on Components, Packaging and Manufacturing Technology

JF - IEEE Transactions on Components, Packaging and Manufacturing Technology

IS - 5

M1 - 6415255

ER -

4-slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8-Gb/s memory controller transceiver

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Keywords

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