TY - GEN
T1 - 3-D modeling of fringing gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs
AU - An, Taeyoon
AU - Kim, Soyoung
PY - 2013
Y1 - 2013
N2 - In this paper, an analytical model for fringing gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs (SNWTs) is proposed. The fringing gate capacitances of the SNWT are divided into three parts: sidewall capacitance Cside; parallel capacitance Cgsd; perpendicular capacitance Cgex. Each capacitance is calculated using the following methods: conformal mapping, integral and non-dimensionalization. The proposed model is verified with a three-dimensional field solver, Raphael. Based on the proposed model, the fringing capacitance can be easily predicted in the vertically and horizontally stacked multi-wire SNWTs.
AB - In this paper, an analytical model for fringing gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs (SNWTs) is proposed. The fringing gate capacitances of the SNWT are divided into three parts: sidewall capacitance Cside; parallel capacitance Cgsd; perpendicular capacitance Cgex. Each capacitance is calculated using the following methods: conformal mapping, integral and non-dimensionalization. The proposed model is verified with a three-dimensional field solver, Raphael. Based on the proposed model, the fringing capacitance can be easily predicted in the vertically and horizontally stacked multi-wire SNWTs.
UR - https://www.scopus.com/pages/publications/84891125310
U2 - 10.1109/SISPAD.2013.6650623
DO - 10.1109/SISPAD.2013.6650623
M3 - Conference contribution
AN - SCOPUS:84891125310
SN - 9781467357364
T3 - International Conference on Simulation of Semiconductor Processes and Devices, SISPAD
SP - 256
EP - 259
BT - 2013 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2013
T2 - 18th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2013
Y2 - 3 September 2013 through 5 September 2013
ER -