TY - GEN
T1 - 128-Channel Multi-Chip Acoustic Hologram Generator
AU - Kustin, John
AU - Kang, Taewook
AU - Song, Seungheun
AU - Naveed, Yahya
AU - Flynn, Michael P.
N1 - Publisher Copyright:
© 2025 JSAP.
PY - 2025
Y1 - 2025
N2 - An ASIC combines a numerically controlled oscillator with reconfigurable amplitude and phase control of 16 channels to synthesize acoustic holograms with a phased array of ultrasonic transmitters. Multiple chiplets operate synchronously to drive arbitrarily many channels. A scalable digital delay line technique, leveraging on-chip SRAM and single-bit noise-shaped bitstreams, realizes area-efficient, high-density, and high-resolution true-time-delay phase shifts. The prototype system employs 8 chiplets to drive a 128-element array for hologram generation.
AB - An ASIC combines a numerically controlled oscillator with reconfigurable amplitude and phase control of 16 channels to synthesize acoustic holograms with a phased array of ultrasonic transmitters. Multiple chiplets operate synchronously to drive arbitrarily many channels. A scalable digital delay line technique, leveraging on-chip SRAM and single-bit noise-shaped bitstreams, realizes area-efficient, high-density, and high-resolution true-time-delay phase shifts. The prototype system employs 8 chiplets to drive a 128-element array for hologram generation.
UR - https://www.scopus.com/pages/publications/105012163919
U2 - 10.23919/VLSITechnologyandCir65189.2025.11075058
DO - 10.23919/VLSITechnologyandCir65189.2025.11075058
M3 - Conference contribution
AN - SCOPUS:105012163919
T3 - Digest of Technical Papers - Symposium on VLSI Technology
BT - 2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025
Y2 - 8 June 2025 through 12 June 2025
ER -