@inproceedings{3978572ba56e412e82468e5dbd7cae30,
title = "11 -bit 1.8uW 40KS/s segmented SAR ADC for sensor applications",
abstract = "This paper proposes an 11-b 40KS/s Successive Approximation Register (SAR) Analog-To-Digital Converter (ADC) structure for sensor applications. Segmented structure is adopted in capacitive DAC to improve the linearity and decrease the power consumption. 500 aF custom-designed unit capacitors are applied in CDAC to reduce the area and to keep the ESX and DNL within 1 LSB of an 11 bit ADC. A prototype ADC was implemented in CMOS 0.18mm technology. This structure consumed 1.8jiW and achieved 67.27-dB SNDR and 83.7-dB SFDR at 40KS/s under a 1.8-V supply. The figure of merit (POM) was 37fJ/conversion-step.",
keywords = "ADC, Linearity', SAR, Segmented DAC, Thermometer codes",
author = "Rikan, \{Behnam Samadpoor\} and Kim, \{Sang Yun\} and Lee, \{Kang Yoon\}",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 13th International SoC Design Conference, ISOCC 2016 ; Conference date: 23-10-2016 Through 26-10-2016",
year = "2016",
month = dec,
day = "27",
doi = "10.1109/ISOCC.2016.7799705",
language = "English",
series = "ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "55--56",
booktitle = "ISOCC 2016 - International SoC Design Conference",
}