11 -bit 1.8uW 40KS/s segmented SAR ADC for sensor applications

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

This paper proposes an 11-b 40KS/s Successive Approximation Register (SAR) Analog-To-Digital Converter (ADC) structure for sensor applications. Segmented structure is adopted in capacitive DAC to improve the linearity and decrease the power consumption. 500 aF custom-designed unit capacitors are applied in CDAC to reduce the area and to keep the ESX and DNL within 1 LSB of an 11 bit ADC. A prototype ADC was implemented in CMOS 0.18mm technology. This structure consumed 1.8jiW and achieved 67.27-dB SNDR and 83.7-dB SFDR at 40KS/s under a 1.8-V supply. The figure of merit (POM) was 37fJ/conversion-step.

Original languageEnglish
Title of host publicationISOCC 2016 - International SoC Design Conference
Subtitle of host publicationSmart SoC for Intelligent Things
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages55-56
Number of pages2
ISBN (Electronic)9781467393089
DOIs
StatePublished - 27 Dec 2016
Event13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of
Duration: 23 Oct 201626 Oct 2016

Publication series

NameISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things

Conference

Conference13th International SoC Design Conference, ISOCC 2016
Country/TerritoryKorea, Republic of
CityJeju
Period23/10/1626/10/16

Keywords

  • ADC
  • Linearity'
  • SAR
  • Segmented DAC
  • Thermometer codes

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