10.76 TOPS/W CNN algorithm circuit using processor-in-memory with 8T-SRAM

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Abstract

Implementing the CNN algorithm on-chip requires a lot of power consumption. To overcome this, research is underway to reduce power consumption by implementing certain operations of digital logic as analog circuits. The purpose of this paper is to propose a structure of new SRAM memory, and to propose CNN algorithm at the circuit level. In this study, 10.76 TOPS/W was achieved.

Original languageEnglish
Title of host publicationProceedings - 2021 IEEE International Conference on Big Data and Smart Computing, BigComp 2021
EditorsHerwig Unger, Jinho Kim, U Kang, Chakchai So-In, Junping Du, Walid Saad, Young-guk Ha, Christian Wagner, Julien Bourgeois, Chanboon Sathitwiriyawong, Hyuk-Yoon Kwon, Carson Leung
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages330-333
Number of pages4
ISBN (Electronic)9781728189246
DOIs
StatePublished - Jan 2021
Event2021 IEEE International Conference on Big Data and Smart Computing, BigComp 2021 - Jeju Island, Korea, Republic of
Duration: 17 Jan 202120 Jan 2021

Publication series

NameProceedings - 2021 IEEE International Conference on Big Data and Smart Computing, BigComp 2021

Conference

Conference2021 IEEE International Conference on Big Data and Smart Computing, BigComp 2021
Country/TerritoryKorea, Republic of
CityJeju Island
Period17/01/2120/01/21

Keywords

  • Analog to Digital Converter
  • Convolutional SRAM
  • Processor In Memory

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