0.37mW/Gb/s low power SLVS transmitter for battery powered applications

Youngkyun Jeong; Yoon Chul Choi; Eun Ji Choi; Seogheon Ham; Kee Won Kwon; Young Hyun Jun; Jung Hoon Chun

doi:10.1109/ISCAS.2012.6271658

0.37mW/Gb/s low power SLVS transmitter for battery powered applications

Youngkyun Jeong
, Yoon Chul Choi
, Eun Ji Choi
, Seogheon Ham
, Kee Won Kwon
, Young Hyun Jun
, Jung Hoon Chun

Department of Semiconductor Systems Engineering

Research output: Contribution to conference › Paper › peer-review

8 Scopus citations

Abstract

A power-efficient voltage-mode transmitter for battery powered mobile applications was designed. The proposed transmitter consists of a power optimized 162 serializer, a data-aligner, 21 multiplexing pre-driver, and an I/O driver with segment control for impedance matching. With scalable low-voltage signaling (SLVS) with the output swing of 200mVp-p and power optimization for digital blocks, 0.37mW/Gb/s power consumption was achieved. The test chip for 4.8 Gb/s interfaces was designed in a 65nm 1.2V supply CMOS logic process. The proposed I/O specifications are appropriate for MIPI M-PHY systems.

Original language	English
Pages	1955-1958
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2012.6271658
State	Published - 2012
Event	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: 20 May 2012 → 23 May 2012

Conference

Conference	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/Territory	Korea, Republic of
City	Seoul
Period	20/05/12 → 23/05/12

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10.1109/ISCAS.2012.6271658

Cite this

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title = "0.37mW/Gb/s low power SLVS transmitter for battery powered applications",

abstract = "A power-efficient voltage-mode transmitter for battery powered mobile applications was designed. The proposed transmitter consists of a power optimized 162 serializer, a data-aligner, 21 multiplexing pre-driver, and an I/O driver with segment control for impedance matching. With scalable low-voltage signaling (SLVS) with the output swing of 200mVp-p and power optimization for digital blocks, 0.37mW/Gb/s power consumption was achieved. The test chip for 4.8 Gb/s interfaces was designed in a 65nm 1.2V supply CMOS logic process. The proposed I/O specifications are appropriate for MIPI M-PHY systems.",

author = "Youngkyun Jeong and Choi, \{Yoon Chul\} and Choi, \{Eun Ji\} and Seogheon Ham and Kwon, \{Kee Won\} and Jun, \{Young Hyun\} and Chun, \{Jung Hoon\}",

year = "2012",

doi = "10.1109/ISCAS.2012.6271658",

language = "English",

pages = "1955--1958",

note = "2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 ; Conference date: 20-05-2012 Through 23-05-2012",

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TY - CONF

T1 - 0.37mW/Gb/s low power SLVS transmitter for battery powered applications

AU - Jeong, Youngkyun

AU - Choi, Yoon Chul

AU - Choi, Eun Ji

AU - Ham, Seogheon

AU - Kwon, Kee Won

AU - Jun, Young Hyun

AU - Chun, Jung Hoon

PY - 2012

Y1 - 2012

N2 - A power-efficient voltage-mode transmitter for battery powered mobile applications was designed. The proposed transmitter consists of a power optimized 162 serializer, a data-aligner, 21 multiplexing pre-driver, and an I/O driver with segment control for impedance matching. With scalable low-voltage signaling (SLVS) with the output swing of 200mVp-p and power optimization for digital blocks, 0.37mW/Gb/s power consumption was achieved. The test chip for 4.8 Gb/s interfaces was designed in a 65nm 1.2V supply CMOS logic process. The proposed I/O specifications are appropriate for MIPI M-PHY systems.

AB - A power-efficient voltage-mode transmitter for battery powered mobile applications was designed. The proposed transmitter consists of a power optimized 162 serializer, a data-aligner, 21 multiplexing pre-driver, and an I/O driver with segment control for impedance matching. With scalable low-voltage signaling (SLVS) with the output swing of 200mVp-p and power optimization for digital blocks, 0.37mW/Gb/s power consumption was achieved. The test chip for 4.8 Gb/s interfaces was designed in a 65nm 1.2V supply CMOS logic process. The proposed I/O specifications are appropriate for MIPI M-PHY systems.

UR - https://www.scopus.com/pages/publications/84866603498

U2 - 10.1109/ISCAS.2012.6271658

DO - 10.1109/ISCAS.2012.6271658

M3 - Paper

AN - SCOPUS:84866603498

SP - 1955

EP - 1958

T2 - 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012

Y2 - 20 May 2012 through 23 May 2012

ER -

0.37mW/Gb/s low power SLVS transmitter for battery powered applications

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