Personal profile
Education
Ph.D. University of Michigan, MI, USA, 2021
M.S. Seoul National University, Korea, 2013
B.S. Seoul National University, Korea, 2011
Professional Experience
2024 - Present, Assistant Professor, Sungkyunkwan University
2021 - 2024, Circuit designer, Apple, CA, USA
2013 - 2016, Circuit designer, Silicon Mitus, Korea
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Collaborations and top research areas from the last five years
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128-Channel Multi-Chip Acoustic Hologram Generator
Kustin, J., Kang, T., Song, S., Naveed, Y. & Flynn, M. P., 2025, 2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025. Institute of Electrical and Electronics Engineers Inc., (Digest of Technical Papers - Symposium on VLSI Technology).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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A 150-MS/s Fully Dynamic SAR-Assisted Pipeline ADC Using a Floating Ring Amplifier and Gain-Enhancing Miller Negative-C
Song, S., Kang, T., Lee, S. & Flynn, M. P., 2025, In: IEEE Open Journal of the Solid-State Circuits Society. 5, p. 145-156 12 p.Research output: Contribution to journal › Article › peer-review
2 Link opens in a new tab Scopus citations -
A Calibration-Free 175MHz Bandwidth 60dB SNDR 6th-Order Bandpass Cascaded Time-Interleaved Noise-Shaping SAR ADC with Optimum Zero Placement
Zhao, Z., Chen, H. W., Song, S., Kang, T. & Flynn, M., 2025, 2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025. Institute of Electrical and Electronics Engineers Inc., (Digest of Technical Papers - Symposium on VLSI Technology).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
2 Link opens in a new tab Scopus citations -
An NS-SAR Quantizer-Based Pipeline Incremental Delta-Sigma ADC Using a Current-Regulated Floating Ring Amplifier and Two-Phase Miller Negative-C
Song, S., Kang, T., Knowlton, A., Lee, S. & Flynn, M. P., 2025, 2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025. Institute of Electrical and Electronics Engineers Inc., (Digest of Technical Papers - Symposium on VLSI Technology).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
2 Link opens in a new tab Scopus citations -
Avalanche: Optimizing Cache Utilization via Matrix Reordering for Sparse Matrix Multiplication Accelerator
Byeon, G., Kim, S., Kim, H., Han, S., Kim, J., Nair, P., Kang, T. & Hong, S., 21 Jun 2025, ISCA 2025 - Proceedings of the 52nd Annual International Symposium on Computer Architecture. Institute of Electrical and Electronics Engineers Inc., p. 1746-1759 14 p. (Proceedings - International Symposium on Computer Architecture).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
Open Access4 Link opens in a new tab Scopus citations