Research output per year
Research output per year
Personal profile
Education
(Ph.D.) in Electrical Engineering , Stanford University, Stanford, U.S.A. (2004)
Professional Experience
Member of Consulting Staff, Digital Implementation, Cadence Design Systems, U.S.A.(2008-2009)
Senior CAD Engineer, Logic Technology Division, Intel Corporation, U.S.A. (2004-2008)
Fingerprint
Dive into the research topics where Soyoung Kim is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Collaborations and top research areas from the last five years
Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
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A Neural-Network-Based Statistical Compact Model Using a Variational Autoencoder for Emerging Transistors
Choi, J. Y., Jeong, H. J., Kim, Y., Parajuli, S., Shrestha, S., Cho, G., Kong, J. T. & Kim, S. Y., 2025, In: IEEE Transactions on Electron Devices. 72, 7, p. 3364-3370 7 p.Research output: Contribution to journal › Article › peer-review
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Co-Optimization of Floorplanning and Decap Placement for TI and PI Based on Machine Learning
Hwang, J. & Kim, S. Y., 2025, 2025 IEEE International Symposium on Electromagnetic Compatibility, Signal and Power Integrity, EMC + SIPI 2025. Institute of Electrical and Electronics Engineers Inc., p. 40-41 2 p. (IEEE International Symposium on Electromagnetic Compatibility).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Device Placement Optimization Based on Sequential Q-Learning Using Local Layout Effect Surrogate Models
Kang, K. & Kim, S., 2025, In: Journal of Semiconductor Technology and Science. 25, 1, p. 82-93 12 p.Research output: Contribution to journal › Article › peer-review
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Hybrid Compact Modeling Strategy: A Fully-Automated and Accurate Compact Model with Physical Consistency
Choi, J. Y., Jeong, H. J., Kong, J. T. & Kim, S. Y., 4 Mar 2025, ASP-DAC 2025 - 30th Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 828-834 7 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Improving the Efficiency of a 10 MHz Voltage Regulator Using a PCB-Embedded Inductor
Kim, G. W., Hwang, J. & Kim, S. Y., Sep 2025, In: Electronics (Switzerland). 14, 18, 3732.Research output: Contribution to journal › Article › peer-review
Open Access